sin_gnt.vhd

来自「宏模块应用实例- 正弦信号发生器的实现」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SIN_GNT IS
   PORT(CLK:IN STD_LOGIC;
        DOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;
ARCHITECTURE DACC OF SIN_GNT IS 
COMPONENT DATA_ROM
   PORT(address : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
        inclock : IN STD_LOGIC;
              q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
    SIGNAL Q1:STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN 
PROCESS(CLK)
BEGIN
   IF CLK'EVENT AND CLK='1' THEN Q1<=Q1+1;
END IF;
END PROCESS;
u1 :data_rom PORT MAP(address=>Q1,q=>DOUT,inclock=>CLK);
END;