altrom_s7g.tdf

宏模块应用实例- 正弦信号发生器的实现

--altrom AD_WIDTH=6 DEVICE_FAMILY="ACEX1K" ENABLE_RUNTIME_MOD="YES" FILE="romd.mif" INSTANCE_NAME="ROM1" MAXIMUM_DEPTH=0 NUMWORDS=64 REGISTERINPUTMODE="ALL" WIDTH=8 address clocki q
--VERSION_BEGIN 5.0 cbx_altrom 2004:11:30:11:30:22:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_lpm_ram_dp 2003:04:24:11:07:36:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
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--  without limitation, that your use is for the sole purpose of 
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--  applicable agreement for further details.


FUNCTION lpm_ram_dp (data[LPM_WIDTH-1..0], rdaddress[LPM_WIDTHAD-1..0], rdclken, rdclock, rden, wraddress[LPM_WIDTHAD-1..0], wrclken, wrclock, wren)
WITH ( 	LPM_FILE,	LPM_INDATA,	LPM_NUMWORDS,	LPM_OUTDATA,	LPM_RDADDRESS_CONTROL,	LPM_WIDTH,	LPM_WIDTHAD,	LPM_WRADDRESS_CONTROL) 
RETURNS ( q[LPM_WIDTH-1..0]);
FUNCTION sld_mod_ram_rom ()
WITH ( 	CVALUE,	IS_DATA_IN_RAM,	IS_READABLE,	NODE_NAME,	NUMWORDS,	SHIFT_COUNT_BITS,	WIDTH_WORD,	WIDTHAD) 
RETURNS ( address[5..0], data_write[7..0], enable_write, tck_usr);

--synthesis_resources = lpm_ram_dp 1 sld_mod_ram_rom 1 
SUBDESIGN altrom_s7g
( 
	address[5..0]	:	input;
	clocki	:	input;
	q[7..0]	:	output;
) 
VARIABLE 
	lpm_ram_dp1 : lpm_ram_dp
		WITH (
			LPM_FILE = "romd.mif",
			LPM_INDATA = "REGISTERED",
			LPM_NUMWORDS = 64,
			LPM_OUTDATA = "UNREGISTERED",
			LPM_RDADDRESS_CONTROL = "REGISTERED",
			LPM_WIDTH = 8,
			LPM_WIDTHAD = 6,
			LPM_WRADDRESS_CONTROL = "REGISTERED"
		);
	mgl_prim2 : sld_mod_ram_rom
		WITH (
			CVALUE = "00000000",
			IS_DATA_IN_RAM = 1,
			IS_READABLE = 0,
			NODE_NAME = 1380928817,
			NUMWORDS = 64,
			SHIFT_COUNT_BITS = 4,
			WIDTH_WORD = 8,
			WIDTHAD = 6
		);

BEGIN 
	lpm_ram_dp1.data[] = mgl_prim2.data_write[];
	lpm_ram_dp1.rdaddress[] = address[];
	lpm_ram_dp1.rdclock = clocki;
	lpm_ram_dp1.rden = B"1";
	lpm_ram_dp1.wraddress[] = mgl_prim2.address[];
	lpm_ram_dp1.wrclock = mgl_prim2.tck_usr;
	lpm_ram_dp1.wren = mgl_prim2.enable_write;
	q[] = lpm_ram_dp1.q[];
END;
--VALID FILE