sin_gnt.map.eqn

宏模块应用实例- 正弦信号发生器的实现

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--K1_q[0] is data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[0]
K1_q[0]_data_in = ~GND;
K1_q[0]_clock_1 = CLK;
K1_q[0]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[0]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5]);
K1_q[0] = MEMORY_SEGMENT(K1_q[0]_data_in, GND, GND, K1_q[0]_clock_1, , , , VCC, K1_q[0]_write_address, K1_q[0]_read_address);


--K1_q[1] is data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[1]
K1_q[1]_data_in = ~GND;
K1_q[1]_clock_1 = CLK;
K1_q[1]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[1]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5]);
K1_q[1] = MEMORY_SEGMENT(K1_q[1]_data_in, GND, GND, K1_q[1]_clock_1, , , , VCC, K1_q[1]_write_address, K1_q[1]_read_address);


--K1_q[2] is data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[2]
K1_q[2]_data_in = ~GND;
K1_q[2]_clock_1 = CLK;
K1_q[2]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[2]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5]);
K1_q[2] = MEMORY_SEGMENT(K1_q[2]_data_in, GND, GND, K1_q[2]_clock_1, , , , VCC, K1_q[2]_write_address, K1_q[2]_read_address);


--K1_q[3] is data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[3]
K1_q[3]_data_in = ~GND;
K1_q[3]_clock_1 = CLK;
K1_q[3]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[3]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5]);
K1_q[3] = MEMORY_SEGMENT(K1_q[3]_data_in, GND, GND, K1_q[3]_clock_1, , , , VCC, K1_q[3]_write_address, K1_q[3]_read_address);


--K1_q[4] is data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[4]
K1_q[4]_data_in = ~GND;
K1_q[4]_clock_1 = CLK;
K1_q[4]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[4]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5]);
K1_q[4] = MEMORY_SEGMENT(K1_q[4]_data_in, GND, GND, K1_q[4]_clock_1, , , , VCC, K1_q[4]_write_address, K1_q[4]_read_address);


--K1_q[5] is data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[5]
K1_q[5]_data_in = ~GND;
K1_q[5]_clock_1 = CLK;
K1_q[5]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[5]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5]);
K1_q[5] = MEMORY_SEGMENT(K1_q[5]_data_in, GND, GND, K1_q[5]_clock_1, , , , VCC, K1_q[5]_write_address, K1_q[5]_read_address);


--K1_q[6] is data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[6]
K1_q[6]_data_in = ~GND;
K1_q[6]_clock_1 = CLK;
K1_q[6]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[6]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5]);
K1_q[6] = MEMORY_SEGMENT(K1_q[6]_data_in, GND, GND, K1_q[6]_clock_1, , , , VCC, K1_q[6]_write_address, K1_q[6]_read_address);


--K1_q[7] is data_rom:u1|altsyncram:altsyncram_component|altrom:rom|altrom_s7g:ag|lpm_ram_dp:lpm_ram_dp1|altdpram:sram|q[7]
K1_q[7]_data_in = ~GND;
K1_q[7]_clock_1 = CLK;
K1_q[7]_write_address = WR_ADDR(~GND, ~GND, ~GND, ~GND, ~GND, ~GND);
K1_q[7]_read_address = RD_ADDR(D1_q[0], D1_q[1], D1_q[2], D1_q[3], D1_q[4], D1_q[5]);
K1_q[7] = MEMORY_SEGMENT(K1_q[7]_data_in, GND, GND, K1_q[7]_clock_1, , , , VCC, K1_q[7]_write_address, K1_q[7]_read_address);


--D1_q[0] is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is up_dn_cntr

D1_q[0]_lut_out = !D1_q[0];
D1_q[0] = DFFEA(D1_q[0]_lut_out, CLK, , , , , );

--D1L51Q is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~0
--operation mode is up_dn_cntr

D1L51Q = D1_q[0];

--D1L3 is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is up_dn_cntr

D1L3 = CARRY(D1_q[0]);


--D1_q[1] is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is up_dn_cntr

D1_q[1]_lut_out = D1_q[1] $ D1L3;
D1_q[1] = DFFEA(D1_q[1]_lut_out, CLK, , , , , );

--D1L71Q is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[1]~1
--operation mode is up_dn_cntr

D1L71Q = D1_q[1];

--D1L5 is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is up_dn_cntr

D1L5 = CARRY(D1_q[1] & (D1L3));


--D1_q[2] is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is up_dn_cntr

D1_q[2]_lut_out = D1_q[2] $ D1L5;
D1_q[2] = DFFEA(D1_q[2]_lut_out, CLK, , , , , );

--D1L91Q is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[2]~2
--operation mode is up_dn_cntr

D1L91Q = D1_q[2];

--D1L7 is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is up_dn_cntr

D1L7 = CARRY(D1_q[2] & (D1L5));


--D1_q[3] is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is up_dn_cntr

D1_q[3]_lut_out = D1_q[3] $ D1L7;
D1_q[3] = DFFEA(D1_q[3]_lut_out, CLK, , , , , );

--D1L12Q is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[3]~3
--operation mode is up_dn_cntr

D1L12Q = D1_q[3];

--D1L9 is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT
--operation mode is up_dn_cntr

D1L9 = CARRY(D1_q[3] & (D1L7));


--D1_q[4] is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4]
--operation mode is up_dn_cntr

D1_q[4]_lut_out = D1_q[4] $ D1L9;
D1_q[4] = DFFEA(D1_q[4]_lut_out, CLK, , , , , );

--D1L32Q is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[4]~4
--operation mode is up_dn_cntr

D1L32Q = D1_q[4];

--D1L11 is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT
--operation mode is up_dn_cntr

D1L11 = CARRY(D1_q[4] & (D1L9));


--D1_q[5] is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5]
--operation mode is up_dn_cntr

D1_q[5]_lut_out = D1_q[5] $ D1L11;
D1_q[5] = DFFEA(D1_q[5]_lut_out, CLK, , , , , );

--D1L52Q is lpm_counter:Q1_rtl_0|alt_counter_f10ke:wysi_counter|q[5]~5
--operation mode is up_dn_cntr

D1L52Q = D1_q[5];


--~GND is ~GND
--operation mode is normal

~GND = GND;

--A1L21 is ~GND~0
--operation mode is normal

A1L21 = GND;


--CLK is CLK
--operation mode is input

CLK = INPUT();


--DOUT[0] is DOUT[0]
--operation mode is output

DOUT[0] = OUTPUT(K1_q[0]);


--DOUT[1] is DOUT[1]
--operation mode is output

DOUT[1] = OUTPUT(K1_q[1]);


--DOUT[2] is DOUT[2]
--operation mode is output

DOUT[2] = OUTPUT(K1_q[2]);


--DOUT[3] is DOUT[3]
--operation mode is output

DOUT[3] = OUTPUT(K1_q[3]);


--DOUT[4] is DOUT[4]
--operation mode is output

DOUT[4] = OUTPUT(K1_q[4]);


--DOUT[5] is DOUT[5]
--operation mode is output

DOUT[5] = OUTPUT(K1_q[5]);


--DOUT[6] is DOUT[6]
--operation mode is output

DOUT[6] = OUTPUT(K1_q[6]);


--DOUT[7] is DOUT[7]
--operation mode is output

DOUT[7] = OUTPUT(K1_q[7]);