cnt60.tan.qmsg

60进制加法器 本人自己编的

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "CNT60.vhd" "" { Text "D:/F盘软件/大三第二学期/EDA/工程/CNT60/CNT60.vhd" 5 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register lpm_counter:BCD1N_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] register BCD10N\[0\] 135.14 MHz 7.4 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 135.14 MHz between source register \"lpm_counter:BCD1N_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" and destination register \"BCD10N\[0\]\" (period= 7.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns + Longest register register " "Info: + Longest register to register delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:BCD1N_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC3_J47 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_J47; Fanout = 5; REG Node = 'lpm_counter:BCD1N_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.200 ns) 2.400 ns LessThan0~23 2 COMB LC7_J47 8 " "Info: 2: + IC(0.200 ns) + CELL(2.200 ns) = 2.400 ns; Loc. = LC7_J47; Fanout = 8; COMB Node = 'LessThan0~23'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.400 ns" { lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] LessThan0~23 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.700 ns) 5.100 ns BCD10N\[0\]~104 3 COMB LC6_J48 3 " "Info: 3: + IC(1.000 ns) + CELL(1.700 ns) = 5.100 ns; Loc. = LC6_J48; Fanout = 3; COMB Node = 'BCD10N\[0\]~104'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.700 ns" { LessThan0~23 BCD10N[0]~104 } "NODE_NAME" } } { "CNT60.vhd" "" { Text "D:/F盘软件/大三第二学期/EDA/工程/CNT60/CNT60.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.300 ns) 5.600 ns BCD10N\[0\] 4 REG LC5_J48 5 " "Info: 4: + IC(0.200 ns) + CELL(0.300 ns) = 5.600 ns; Loc. = LC5_J48; Fanout = 5; REG Node = 'BCD10N\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.500 ns" { BCD10N[0]~104 BCD10N[0] } "NODE_NAME" } } { "CNT60.vhd" "" { Text "D:/F盘软件/大三第二学期/EDA/工程/CNT60/CNT60.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.200 ns ( 75.00 % ) " "Info: Total cell delay = 4.200 ns ( 75.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 25.00 % ) " "Info: Total interconnect delay = 1.400 ns ( 25.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.600 ns" { lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] LessThan0~23 BCD10N[0]~104 BCD10N[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.600 ns" { lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] LessThan0~23 BCD10N[0]~104 BCD10N[0] } { 0.000ns 0.200ns 1.000ns 0.200ns } { 0.000ns 2.200ns 1.700ns 0.300ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_184 10 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_184; Fanout = 10; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CNT60.vhd" "" { Text "D:/F盘软件/大三第二学期/EDA/工程/CNT60/CNT60.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns BCD10N\[0\] 2 REG LC5_J48 5 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_J48; Fanout = 5; REG Node = 'BCD10N\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK BCD10N[0] } "NODE_NAME" } } { "CNT60.vhd" "" { Text "D:/F盘软件/大三第二学期/EDA/工程/CNT60/CNT60.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK BCD10N[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out BCD10N[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_184 10 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_184; Fanout = 10; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CNT60.vhd" "" { Text "D:/F盘软件/大三第二学期/EDA/工程/CNT60/CNT60.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns lpm_counter:BCD1N_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC3_J47 5 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_J47; Fanout = 5; REG Node = 'lpm_counter:BCD1N_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK BCD10N[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out BCD10N[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "CNT60.vhd" "" { Text "D:/F盘软件/大三第二学期/EDA/工程/CNT60/CNT60.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.600 ns" { lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] LessThan0~23 BCD10N[0]~104 BCD10N[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.600 ns" { lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] LessThan0~23 BCD10N[0]~104 BCD10N[0] } { 0.000ns 0.200ns 1.000ns 0.200ns } { 0.000ns 2.200ns 1.700ns 0.300ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK BCD10N[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out BCD10N[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK BCD1WR\[1\] lpm_counter:BCD1N_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 18.100 ns register " "Info: tco from clock \"CLK\" to destination pin \"BCD1WR\[1\]\" through register \"lpm_counter:BCD1N_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]\" is 18.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.900 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns CLK 1 CLK PIN_184 10 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_184; Fanout = 10; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "CNT60.vhd" "" { Text "D:/F盘软件/大三第二学期/EDA/工程/CNT60/CNT60.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns lpm_counter:BCD1N_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 2 REG LC4_J47 5 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_J47; Fanout = 5; REG Node = 'lpm_counter:BCD1N_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { CLK lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.100 ns + Longest register pin " "Info: + Longest register to pin delay is 15.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:BCD1N_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\] 1 REG LC4_J47 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_J47; Fanout = 5; REG Node = 'lpm_counter:BCD1N_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(1.700 ns) 3.700 ns BCD1WR\[1\]~0 2 COMB LC5_J27 1 " "Info: 2: + IC(2.000 ns) + CELL(1.700 ns) = 3.700 ns; Loc. = LC5_J27; Fanout = 1; COMB Node = 'BCD1WR\[1\]~0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.700 ns" { lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] BCD1WR[1]~0 } "NODE_NAME" } } { "CNT60.vhd" "" { Text "D:/F盘软件/大三第二学期/EDA/工程/CNT60/CNT60.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(8.600 ns) 15.100 ns BCD1WR\[1\] 3 PIN PIN_31 0 " "Info: 3: + IC(2.800 ns) + CELL(8.600 ns) = 15.100 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'BCD1WR\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.400 ns" { BCD1WR[1]~0 BCD1WR[1] } "NODE_NAME" } } { "CNT60.vhd" "" { Text "D:/F盘软件/大三第二学期/EDA/工程/CNT60/CNT60.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.300 ns ( 68.21 % ) " "Info: Total cell delay = 10.300 ns ( 68.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.800 ns ( 31.79 % ) " "Info: Total interconnect delay = 4.800 ns ( 31.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.100 ns" { lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] BCD1WR[1]~0 BCD1WR[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.100 ns" { lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] BCD1WR[1]~0 BCD1WR[1] } { 0.000ns 2.000ns 2.800ns } { 0.000ns 1.700ns 8.600ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { CLK lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { CLK CLK~out lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.100 ns" { lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] BCD1WR[1]~0 BCD1WR[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "15.100 ns" { lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] BCD1WR[1]~0 BCD1WR[1] } { 0.000ns 2.000ns 2.800ns } { 0.000ns 1.700ns 8.600ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 11 16:46:23 2008 " "Info: Processing ended: Sun May 11 16:46:23 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}