cnt60.vhd

60进制加法器 本人自己编的

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT60 IS
   PORT(CLK,CLEAR,UNIT:IN STD_LOGIC;
        A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        BCD1WR:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        BCD10WR:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END CNT60;
ARCHITECTURE ONE OF CNT60 IS

BEGIN
  PROCESS(CLK,CLEAR,UNIT,A)
    VARIABLE BCD1N:STD_LOGIC_VECTOR(3 DOWNTO 0);
    VARIABLE BCD10N:STD_LOGIC_VECTOR(2 DOWNTO 0);
   BEGIN
    IF CLEAR='1' THEN 
     BCD1N :="0000";
     BCD10N :="000";
    ELSIF UNIT='1' THEN 
     BCD1N :=A;
     BCD10N :=A(2 DOWNTO 0);
    ELSIF CLK'EVENT AND CLK='1' THEN
       IF BCD1N>="1001" THEN
          BCD1N :="0000";
         IF BCD10N>="101" THEN
            BCD10N :="000";
         ELSE
            BCD10N :=BCD10N+1;
         END IF;
       ELSE 
          BCD1N :=BCD1N+1;
       END IF;
    END IF;
       BCD1WR<=BCD1N;
       BCD10WR<=BCD10N;
  END PROCESS;
END ONE;