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📄 cnt60.map.eqn

📁 60进制加法器 本人自己编的
💻 EQN
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--C1_q[0] is lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0]
--operation mode is clrb_cntr

C1_q[0]_lut_out = (!C1_q[0]) & A1L03;
C1_q[0] = DFFEA(C1_q[0]_lut_out, CLK, !CLEAR, , , A[0], UNIT);

--C1L11Q is lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0]~0
--operation mode is clrb_cntr

C1L11Q = C1_q[0];

--C1L3 is lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

C1L3 = CARRY(C1_q[0]);


--C1_q[1] is lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

C1_q[1]_lut_out = (C1_q[1] $ C1L3) & A1L03;
C1_q[1] = DFFEA(C1_q[1]_lut_out, CLK, !CLEAR, , , A[1], UNIT);

--C1L31Q is lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1]~1
--operation mode is clrb_cntr

C1L31Q = C1_q[1];

--C1L5 is lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

C1L5 = CARRY(C1_q[1] & (C1L3));


--C1_q[2] is lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[2]
--operation mode is clrb_cntr

C1_q[2]_lut_out = (C1_q[2] $ C1L5) & A1L03;
C1_q[2] = DFFEA(C1_q[2]_lut_out, CLK, !CLEAR, , , A[2], UNIT);

--C1L51Q is lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[2]~2
--operation mode is clrb_cntr

C1L51Q = C1_q[2];

--C1L7 is lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT
--operation mode is clrb_cntr

C1L7 = CARRY(C1_q[2] & (C1L5));


--C1_q[3] is lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[3]
--operation mode is clrb_cntr

C1_q[3]_lut_out = (C1_q[3] $ C1L7) & A1L03;
C1_q[3] = DFFEA(C1_q[3]_lut_out, CLK, !CLEAR, , , A[3], UNIT);

--C1L71Q is lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[3]~3
--operation mode is clrb_cntr

C1L71Q = C1_q[3];


--BCD10N[0] is BCD10N[0]
--operation mode is normal

BCD10N[0]_lut_out = !BCD10N[0] & (A1L13);
BCD10N[0] = DFFEA(BCD10N[0]_lut_out, CLK, !CLEAR, , A1L31, A[0], UNIT);

--A1L41Q is BCD10N[0]~107
--operation mode is normal

A1L41Q = BCD10N[0];


--BCD10N[1] is BCD10N[1]
--operation mode is normal

BCD10N[1]_lut_out = A1L02;
BCD10N[1] = DFFEA(BCD10N[1]_lut_out, CLK, !CLEAR, , A1L31, A[1], UNIT);

--A1L71Q is BCD10N[1]~108
--operation mode is normal

A1L71Q = BCD10N[1];


--BCD10N[2] is BCD10N[2]
--operation mode is normal

BCD10N[2]_lut_out = !A1L12;
BCD10N[2] = DFFEA(BCD10N[2]_lut_out, CLK, !CLEAR, , A1L31, A[2], UNIT);

--A1L91Q is BCD10N[2]~109
--operation mode is normal

A1L91Q = BCD10N[2];


--A1L03 is LessThan~57
--operation mode is normal

A1L03 = !C1_q[0] & !C1_q[1] & !C1_q[2] # !C1_q[3];

--A1L23 is LessThan~59
--operation mode is normal

A1L23 = !C1_q[0] & !C1_q[1] & !C1_q[2] # !C1_q[3];


--A1L13 is LessThan~58
--operation mode is normal

A1L13 = !BCD10N[0] & !BCD10N[1] # !BCD10N[2];

--A1L33 is LessThan~60
--operation mode is normal

A1L33 = !BCD10N[0] & !BCD10N[1] # !BCD10N[2];


--A1L02 is BCD10N~100
--operation mode is normal

A1L02 = !BCD10N[2] & (BCD10N[0] $ BCD10N[1]);

--A1L22 is BCD10N~110
--operation mode is normal

A1L22 = !BCD10N[2] & (BCD10N[0] $ BCD10N[1]);


--A1L12 is BCD10N~101
--operation mode is normal

A1L12 = BCD10N[2] & (BCD10N[0] # BCD10N[1]) # !BCD10N[2] & (!BCD10N[1] # !BCD10N[0]);

--A1L32 is BCD10N~111
--operation mode is normal

A1L32 = BCD10N[2] & (BCD10N[0] # BCD10N[1]) # !BCD10N[2] & (!BCD10N[1] # !BCD10N[0]);


--A1L31 is BCD10N[0]~104
--operation mode is normal

A1L31 = !A1L03;

--A1L51 is BCD10N[0]~112
--operation mode is normal

A1L51 = !A1L03;


--CLEAR is CLEAR
--operation mode is input

CLEAR = INPUT();


--UNIT is UNIT
--operation mode is input

UNIT = INPUT();


--CLK is CLK
--operation mode is input

CLK = INPUT();


--A[3] is A[3]
--operation mode is input

A[3] = INPUT();


--A[0] is A[0]
--operation mode is input

A[0] = INPUT();


--A[1] is A[1]
--operation mode is input

A[1] = INPUT();


--A[2] is A[2]
--operation mode is input

A[2] = INPUT();


--BCD1WR[0] is BCD1WR[0]
--operation mode is output

BCD1WR[0] = OUTPUT(C1_q[0]);


--BCD1WR[1] is BCD1WR[1]
--operation mode is output

BCD1WR[1] = OUTPUT(C1_q[1]);


--BCD1WR[2] is BCD1WR[2]
--operation mode is output

BCD1WR[2] = OUTPUT(C1_q[2]);


--BCD1WR[3] is BCD1WR[3]
--operation mode is output

BCD1WR[3] = OUTPUT(C1_q[3]);


--BCD10WR[0] is BCD10WR[0]
--operation mode is output

BCD10WR[0] = OUTPUT(BCD10N[0]);


--BCD10WR[1] is BCD10WR[1]
--operation mode is output

BCD10WR[1] = OUTPUT(BCD10N[1]);


--BCD10WR[2] is BCD10WR[2]
--operation mode is output

BCD10WR[2] = OUTPUT(BCD10N[2]);


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