📄 cnt60.tan.rpt
字号:
; N/A ; 144.93 MHz ( period = 6.900 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; BCD10N[1] ; CLK ; CLK ; None ; None ; 5.100 ns ;
; N/A ; 144.93 MHz ( period = 6.900 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; BCD10N[2] ; CLK ; CLK ; None ; None ; 5.100 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; CLK ; CLK ; None ; None ; 3.900 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; CLK ; CLK ; None ; None ; 3.900 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; CLK ; CLK ; None ; None ; 3.900 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; CLK ; CLK ; None ; None ; 3.900 ns ;
; N/A ; 181.82 MHz ( period = 5.500 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; CLK ; CLK ; None ; None ; 3.700 ns ;
; N/A ; 181.82 MHz ( period = 5.500 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; CLK ; CLK ; None ; None ; 3.700 ns ;
; N/A ; 181.82 MHz ( period = 5.500 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; CLK ; CLK ; None ; None ; 3.700 ns ;
; N/A ; 181.82 MHz ( period = 5.500 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; CLK ; CLK ; None ; None ; 3.700 ns ;
; N/A ; 185.19 MHz ( period = 5.400 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; CLK ; CLK ; None ; None ; 3.600 ns ;
; N/A ; 185.19 MHz ( period = 5.400 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; CLK ; CLK ; None ; None ; 3.600 ns ;
; N/A ; 185.19 MHz ( period = 5.400 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; CLK ; CLK ; None ; None ; 3.600 ns ;
; N/A ; 185.19 MHz ( period = 5.400 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; CLK ; CLK ; None ; None ; 3.600 ns ;
; N/A ; 192.31 MHz ( period = 5.200 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; CLK ; CLK ; None ; None ; 3.400 ns ;
; N/A ; 192.31 MHz ( period = 5.200 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; CLK ; CLK ; None ; None ; 3.400 ns ;
; N/A ; 192.31 MHz ( period = 5.200 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; CLK ; CLK ; None ; None ; 3.400 ns ;
; N/A ; 192.31 MHz ( period = 5.200 ns ) ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; CLK ; CLK ; None ; None ; 3.400 ns ;
; N/A ; 192.31 MHz ( period = 5.200 ns ) ; BCD10N[0] ; BCD10N[0] ; CLK ; CLK ; None ; None ; 3.400 ns ;
; N/A ; 192.31 MHz ( period = 5.200 ns ) ; BCD10N[0] ; BCD10N[1] ; CLK ; CLK ; None ; None ; 3.400 ns ;
; N/A ; 192.31 MHz ( period = 5.200 ns ) ; BCD10N[2] ; BCD10N[2] ; CLK ; CLK ; None ; None ; 3.400 ns ;
; N/A ; 196.08 MHz ( period = 5.100 ns ) ; BCD10N[1] ; BCD10N[0] ; CLK ; CLK ; None ; None ; 3.300 ns ;
; N/A ; 196.08 MHz ( period = 5.100 ns ) ; BCD10N[1] ; BCD10N[1] ; CLK ; CLK ; None ; None ; 3.300 ns ;
; N/A ; 196.08 MHz ( period = 5.100 ns ) ; BCD10N[0] ; BCD10N[2] ; CLK ; CLK ; None ; None ; 3.300 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; BCD10N[2] ; BCD10N[0] ; CLK ; CLK ; None ; None ; 3.100 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; BCD10N[2] ; BCD10N[1] ; CLK ; CLK ; None ; None ; 3.100 ns ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; BCD10N[1] ; BCD10N[2] ; CLK ; CLK ; None ; None ; 3.100 ns ;
+-------+------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------------------------------------------------------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------------------------------------------------------------+------------+------------+
; N/A ; None ; 18.100 ns ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; BCD1WR[1] ; CLK ;
; N/A ; None ; 16.100 ns ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; BCD1WR[2] ; CLK ;
; N/A ; None ; 16.000 ns ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; BCD1WR[3] ; CLK ;
; N/A ; None ; 14.200 ns ; lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; BCD1WR[0] ; CLK ;
; N/A ; None ; 14.100 ns ; BCD10N[0] ; BCD10WR[0] ; CLK ;
; N/A ; None ; 12.300 ns ; BCD10N[2] ; BCD10WR[2] ; CLK ;
; N/A ; None ; 12.300 ns ; BCD10N[1] ; BCD10WR[1] ; CLK ;
+-------+--------------+------------+-------------------------------------------------------------+------------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sun May 11 16:46:21 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off CNT60 -c CNT60
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 135.14 MHz between source register "lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" and destination register "BCD10N[0]" (period= 7.4 ns)
Info: + Longest register to register delay is 5.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_J47; Fanout = 5; REG Node = 'lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
Info: 2: + IC(0.200 ns) + CELL(2.200 ns) = 2.400 ns; Loc. = LC7_J47; Fanout = 8; COMB Node = 'LessThan0~23'
Info: 3: + IC(1.000 ns) + CELL(1.700 ns) = 5.100 ns; Loc. = LC6_J48; Fanout = 3; COMB Node = 'BCD10N[0]~104'
Info: 4: + IC(0.200 ns) + CELL(0.300 ns) = 5.600 ns; Loc. = LC5_J48; Fanout = 5; REG Node = 'BCD10N[0]'
Info: Total cell delay = 4.200 ns ( 75.00 % )
Info: Total interconnect delay = 1.400 ns ( 25.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "CLK" to destination register is 1.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_184; Fanout = 10; CLK Node = 'CLK'
Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC5_J48; Fanout = 5; REG Node = 'BCD10N[0]'
Info: Total cell delay = 0.500 ns ( 26.32 % )
Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: - Longest clock path from clock "CLK" to source register is 1.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_184; Fanout = 10; CLK Node = 'CLK'
Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_J47; Fanout = 5; REG Node = 'lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
Info: Total cell delay = 0.500 ns ( 26.32 % )
Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Micro setup delay of destination is 0.700 ns
Info: tco from clock "CLK" to destination pin "BCD1WR[1]" through register "lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1]" is 18.100 ns
Info: + Longest clock path from clock "CLK" to source register is 1.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_184; Fanout = 10; CLK Node = 'CLK'
Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_J47; Fanout = 5; REG Node = 'lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1]'
Info: Total cell delay = 0.500 ns ( 26.32 % )
Info: Total interconnect delay = 1.400 ns ( 73.68 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Longest register to pin delay is 15.100 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_J47; Fanout = 5; REG Node = 'lpm_counter:BCD1N_rtl_0|alt_counter_f10ke:wysi_counter|q[1]'
Info: 2: + IC(2.000 ns) + CELL(1.700 ns) = 3.700 ns; Loc. = LC5_J27; Fanout = 1; COMB Node = 'BCD1WR[1]~0'
Info: 3: + IC(2.800 ns) + CELL(8.600 ns) = 15.100 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'BCD1WR[1]'
Info: Total cell delay = 10.300 ns ( 68.21 % )
Info: Total interconnect delay = 4.800 ns ( 31.79 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Sun May 11 16:46:23 2008
Info: Elapsed time: 00:00:04
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