📄 watch.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity watch is
Port( clk,scanclk,clr,m_add,h_add : in STD_LOGIC;
Row : out STD_LOGIC_VECTOR(7 downto 0);
led : out STD_LOGIC_VECTOR(7 downto 0));
end watch;
architecture behave of watch is
SIGNAL clk_div : STD_LOGIC_VECTOR(2 downto 0);
SIGNAL h1,h0,m1,m0,s1,s0 : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL num : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL disp : STD_LOGIC_VECTOR(2 downto 0);
SIGNAL m_carry : STD_LOGIC;
Begin
Ps:process(clk,clr)
Begin
If (clr='0') then
S0<="0000";
S1<="0000";
Elsif rising_edge(clk) then
If s0="1001" then
S0<="0000";
Else
S0<= S0+'1';
End if;
If ((s1="0101") and (s0="1001")) then
s1<="0000";
elsif s0="1001" then
S1<=s1+'1';
End if;
End if;
End process ps;
Pm:process(clk,clr,s1,s0,m_add)
Begin
If clr='0' then
m0<="0001";
m1<="0000";
Elsif (rising_edge(clk)) then
If (((s1="0101") and (s0="1001")) or (m_add='1')) then
If (m0="1001") then
m0<="0000";
Else
m0<=m0+'1';
End if;
If ((m1="0101") and (m0="1001")) then
M1<="0000";
Elsif m0="1001" then
M1<=m1+'1';
End if;
End if;
End if;
End process pm;
Ph:process(clk,clr,m1,m0,s1,s0,h_add)
Begin
If clr='0' then
h0<="0001";
h1<="0000";
Elsif (rising_edge(clk)) then
If (((s1="0101") and (s0="1001") and (m1="0101") and (m0="1001")) or (h_add='1')) then
If ((h1="0001") and (h0="0010")) or ((h0="1001")) then
h0<="0000";
Else
h0<=h0+'1';
End if;
If ((h1="0001") and (h0="0010")) then
h1<="0000";
Elsif h0="1001" then
h1<=h1+'1';
End if;
End if;
End if;
End process ph;
scan:process(scanclk) --动态
Begin
If rising_edge(scanclk) then
Disp<=disp+'1';
End if;
End process scan;
selec:process(disp)
Begin
If disp="000"then
Row<="10000000"; num<=h1;
Elsif disp="001" then
Row<="01000000"; num<=h0;
Elsif disp="010" then
Row<="00010000"; num<=m1;
Elsif disp="011" then
Row<="00001000"; num<=m0;
Elsif disp="100" then
Row<="00000010"; num<=s1;
Elsif disp="101" then
Row<="00000001"; num<=s0;
Elsif disp="110" then
Row<="00100000"; num<="1010";
Elsif disp="111" then
Row<="00000100"; num<="1010";
End if;
End process selec;
With num select
Led<="01100000" when "0001",
"11011010" when "0010",
"11110010" when "0011",
"01100110" when "0100",
"10110110" when "0101",
"10111110" when "0110",
"11100000" when "0111",
"11111110" when "1000",
"11110110" when "1001",
"00000010" when "1010",
"11111100" when others;
End behave;
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