vga.map.qmsg

关于VGA显示的vhdl源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 09 09:54:55 2007 " "Info: Processing started: Tue Jan 09 09:54:55 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off vga -c vga " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga -c vga" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "10 vga.v(33) " "Warning (10229): Verilog HDL Expression warning at vga.v(33): truncated literal to match 10 bits" {  } { { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 33 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "10 vga.v(46) " "Warning (10229): Verilog HDL Expression warning at vga.v(46): truncated literal to match 10 bits" {  } { { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 46 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file vga.v" { { "Info" "ISGN_ENTITY_NAME" "1 vga " "Info: Found entity 1: vga" {  } { { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "vga " "Info: Elaborating entity \"vga\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga.v(36) " "Warning (10230): Verilog HDL assignment warning at vga.v(36): truncated value with size 32 to match size of target (1)" {  } { { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 36 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 vga.v(49) " "Warning (10230): Verilog HDL assignment warning at vga.v(49): truncated value with size 32 to match size of target (1)" {  } { { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 49 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 vga.v(62) " "Warning (10230): Verilog HDL assignment warning at vga.v(62): truncated value with size 32 to match size of target (10)" {  } { { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 62 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 vga.v(80) " "Warning (10230): Verilog HDL assignment warning at vga.v(80): truncated value with size 32 to match size of target (10)" {  } { { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 80 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "clk1 clk2 " "Info: Duplicate register \"clk1\" merged to single register \"clk2\"" {  } { { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 25 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "67 " "Info: Implemented 67 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "60 " "Info: Implemented 60 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 09 09:54:56 2007 " "Info: Processing ended: Tue Jan 09 09:54:56 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}