vga.tan.qmsg

关于VGA显示的vhdl源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register x_cnt\[4\] register vga_blue 126.74 MHz 7.89 ns Internal " "Info: Clock \"clock\" has Internal fmax of 126.74 MHz between source register \"x_cnt\[4\]\" and destination register \"vga_blue\" (period= 7.89 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.922 ns + Longest register register " "Info: + Longest register to register delay is 3.922 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns x_cnt\[4\] 1 REG LCFF_X19_Y9_N15 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y9_N15; Fanout = 8; REG Node = 'x_cnt\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { x_cnt[4] } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(0.615 ns) 1.315 ns always10~211 2 COMB LCCOMB_X20_Y9_N30 3 " "Info: 2: + IC(0.700 ns) + CELL(0.615 ns) = 1.315 ns; Loc. = LCCOMB_X20_Y9_N30; Fanout = 3; COMB Node = 'always10~211'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.315 ns" { x_cnt[4] always10~211 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.370 ns) 2.279 ns vga_blue~247 3 COMB LCCOMB_X21_Y9_N30 1 " "Info: 3: + IC(0.594 ns) + CELL(0.370 ns) = 2.279 ns; Loc. = LCCOMB_X21_Y9_N30; Fanout = 1; COMB Node = 'vga_blue~247'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.964 ns" { always10~211 vga_blue~247 } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.584 ns) + CELL(0.206 ns) 3.069 ns vga_blue~248 4 COMB LCCOMB_X20_Y9_N16 1 " "Info: 4: + IC(0.584 ns) + CELL(0.206 ns) = 3.069 ns; Loc. = LCCOMB_X20_Y9_N16; Fanout = 1; COMB Node = 'vga_blue~248'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.790 ns" { vga_blue~247 vga_blue~248 } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.375 ns) + CELL(0.370 ns) 3.814 ns vga_blue~250 5 COMB LCCOMB_X20_Y9_N22 1 " "Info: 5: + IC(0.375 ns) + CELL(0.370 ns) = 3.814 ns; Loc. = LCCOMB_X20_Y9_N22; Fanout = 1; COMB Node = 'vga_blue~250'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.745 ns" { vga_blue~248 vga_blue~250 } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.922 ns vga_blue 6 REG LCFF_X20_Y9_N23 1 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 3.922 ns; Loc. = LCFF_X20_Y9_N23; Fanout = 1; REG Node = 'vga_blue'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { vga_blue~250 vga_blue } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.669 ns ( 42.55 % ) " "Info: Total cell delay = 1.669 ns ( 42.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.253 ns ( 57.45 % ) " "Info: Total interconnect delay = 2.253 ns ( 57.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.922 ns" { x_cnt[4] always10~211 vga_blue~247 vga_blue~248 vga_blue~250 vga_blue } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.922 ns" { x_cnt[4] always10~211 vga_blue~247 vga_blue~248 vga_blue~250 vga_blue } { 0.000ns 0.700ns 0.594ns 0.584ns 0.375ns 0.000ns } { 0.000ns 0.615ns 0.370ns 0.206ns 0.370ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.704 ns - Smallest " "Info: - Smallest clock skew is -3.704 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.764 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.764 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clock 1 CLK PIN_88 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_88; Fanout = 1; CLK Node = 'clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.000 ns) 1.250 ns clock~clkctrl 2 COMB CLKCTRL_G7 11 " "Info: 2: + IC(0.140 ns) + CELL(0.000 ns) = 1.250 ns; Loc. = CLKCTRL_G7; Fanout = 11; COMB Node = 'clock~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.140 ns" { clock clock~clkctrl } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.848 ns) + CELL(0.666 ns) 2.764 ns vga_blue 3 REG LCFF_X20_Y9_N23 1 " "Info: 3: + IC(0.848 ns) + CELL(0.666 ns) = 2.764 ns; Loc. = LCFF_X20_Y9_N23; Fanout = 1; REG Node = 'vga_blue'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.514 ns" { clock~clkctrl vga_blue } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 64.25 % ) " "Info: Total cell delay = 1.776 ns ( 64.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.988 ns ( 35.75 % ) " "Info: Total interconnect delay = 0.988 ns ( 35.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.764 ns" { clock clock~clkctrl vga_blue } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.764 ns" { clock clock~combout clock~clkctrl vga_blue } { 0.000ns 0.000ns 0.140ns 0.848ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 6.468 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 6.468 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clock 1 CLK PIN_88 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_88; Fanout = 1; CLK Node = 'clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.000 ns) 1.250 ns clock~clkctrl 2 COMB CLKCTRL_G7 11 " "Info: 2: + IC(0.140 ns) + CELL(0.000 ns) = 1.250 ns; Loc. = CLKCTRL_G7; Fanout = 11; COMB Node = 'clock~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.140 ns" { clock clock~clkctrl } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.850 ns) + CELL(0.970 ns) 3.070 ns clk2 3 REG LCFF_X22_Y9_N29 2 " "Info: 3: + IC(0.850 ns) + CELL(0.970 ns) = 3.070 ns; Loc. = LCFF_X22_Y9_N29; Fanout = 2; REG Node = 'clk2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.820 ns" { clock~clkctrl clk2 } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.884 ns) + CELL(0.000 ns) 4.954 ns clk2~clkctrl 4 COMB CLKCTRL_G4 20 " "Info: 4: + IC(1.884 ns) + CELL(0.000 ns) = 4.954 ns; Loc. = CLKCTRL_G4; Fanout = 20; COMB Node = 'clk2~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.884 ns" { clk2 clk2~clkctrl } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.848 ns) + CELL(0.666 ns) 6.468 ns x_cnt\[4\] 5 REG LCFF_X19_Y9_N15 8 " "Info: 5: + IC(0.848 ns) + CELL(0.666 ns) = 6.468 ns; Loc. = LCFF_X19_Y9_N15; Fanout = 8; REG Node = 'x_cnt\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.514 ns" { clk2~clkctrl x_cnt[4] } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.746 ns ( 42.46 % ) " "Info: Total cell delay = 2.746 ns ( 42.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.722 ns ( 57.54 % ) " "Info: Total interconnect delay = 3.722 ns ( 57.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.468 ns" { clock clock~clkctrl clk2 clk2~clkctrl x_cnt[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.468 ns" { clock clock~combout clock~clkctrl clk2 clk2~clkctrl x_cnt[4] } { 0.000ns 0.000ns 0.140ns 0.850ns 1.884ns 0.848ns } { 0.000ns 1.110ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.764 ns" { clock clock~clkctrl vga_blue } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.764 ns" { clock clock~combout clock~clkctrl vga_blue } { 0.000ns 0.000ns 0.140ns 0.848ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.468 ns" { clock clock~clkctrl clk2 clk2~clkctrl x_cnt[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.468 ns" { clock clock~combout clock~clkctrl clk2 clk2~clkctrl x_cnt[4] } { 0.000ns 0.000ns 0.140ns 0.850ns 1.884ns 0.848ns } { 0.000ns 1.110ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.922 ns" { x_cnt[4] always10~211 vga_blue~247 vga_blue~248 vga_blue~250 vga_blue } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.922 ns" { x_cnt[4] always10~211 vga_blue~247 vga_blue~248 vga_blue~250 vga_blue } { 0.000ns 0.700ns 0.594ns 0.584ns 0.375ns 0.000ns } { 0.000ns 0.615ns 0.370ns 0.206ns 0.370ns 0.108ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.764 ns" { clock clock~clkctrl vga_blue } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.764 ns" { clock clock~combout clock~clkctrl vga_blue } { 0.000ns 0.000ns 0.140ns 0.848ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.468 ns" { clock clock~clkctrl clk2 clk2~clkctrl x_cnt[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.468 ns" { clock clock~combout clock~clkctrl clk2 clk2~clkctrl x_cnt[4] } { 0.000ns 0.000ns 0.140ns 0.850ns 1.884ns 0.848ns } { 0.000ns 1.110ns 0.000ns 0.970ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock green green~reg0 9.111 ns register " "Info: tco from clock \"clock\" to destination pin \"green\" through register \"green~reg0\" is 9.111 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.765 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.765 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.110 ns) 1.110 ns clock 1 CLK PIN_88 1 " "Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_88; Fanout = 1; CLK Node = 'clock'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.000 ns) 1.250 ns clock~clkctrl 2 COMB CLKCTRL_G7 11 " "Info: 2: + IC(0.140 ns) + CELL(0.000 ns) = 1.250 ns; Loc. = CLKCTRL_G7; Fanout = 11; COMB Node = 'clock~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.140 ns" { clock clock~clkctrl } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.849 ns) + CELL(0.666 ns) 2.765 ns green~reg0 3 REG LCFF_X21_Y9_N25 1 " "Info: 3: + IC(0.849 ns) + CELL(0.666 ns) = 2.765 ns; Loc. = LCFF_X21_Y9_N25; Fanout = 1; REG Node = 'green~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.515 ns" { clock~clkctrl green~reg0 } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.776 ns ( 64.23 % ) " "Info: Total cell delay = 1.776 ns ( 64.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.989 ns ( 35.77 % ) " "Info: Total interconnect delay = 0.989 ns ( 35.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { clock clock~clkctrl green~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.765 ns" { clock clock~combout clock~clkctrl green~reg0 } { 0.000ns 0.000ns 0.140ns 0.849ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 135 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.042 ns + Longest register pin " "Info: + Longest register to pin delay is 6.042 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns green~reg0 1 REG LCFF_X21_Y9_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y9_N25; Fanout = 1; REG Node = 'green~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { green~reg0 } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.806 ns) + CELL(3.236 ns) 6.042 ns green 2 PIN PIN_136 0 " "Info: 2: + IC(2.806 ns) + CELL(3.236 ns) = 6.042 ns; Loc. = PIN_136; Fanout = 0; PIN Node = 'green'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.042 ns" { green~reg0 green } "NODE_NAME" } } { "vga.v" "" { Text "D:/NIOSII_LAB/vga_display/vga.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 53.56 % ) " "Info: Total cell delay = 3.236 ns ( 53.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.806 ns ( 46.44 % ) " "Info: Total interconnect delay = 2.806 ns ( 46.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.042 ns" { green~reg0 green } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.042 ns" { green~reg0 green } { 0.000ns 2.806ns } { 0.000ns 3.236ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { clock clock~clkctrl green~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.765 ns" { clock clock~combout clock~clkctrl green~reg0 } { 0.000ns 0.000ns 0.140ns 0.849ns } { 0.000ns 1.110ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.042 ns" { green~reg0 green } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.042 ns" { green~reg0 green } { 0.000ns 2.806ns } { 0.000ns 3.236ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 09 09:55:12 2007 " "Info: Processing ended: Tue Jan 09 09:55:12 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}