vga.hier_info

关于VGA显示的vhdl源代码

|vga
rst_n => x_cnt[8].ACLR
rst_n => x_cnt[7].ACLR
rst_n => x_cnt[6].ACLR
rst_n => x_cnt[5].ACLR
rst_n => x_cnt[4].ACLR
rst_n => x_cnt[3].ACLR
rst_n => x_cnt[2].ACLR
rst_n => x_cnt[1].ACLR
rst_n => x_cnt[0].ACLR
rst_n => vsyn~reg0.ACLR
rst_n => x_cnt[9].ACLR
rst_n => red~reg0.ACLR
rst_n => hsyn~reg0.ACLR
rst_n => green~reg0.ACLR
rst_n => blue~reg0.ACLR
rst_n => clk2.ACLR
rst_n => y_cnt[8].ACLR
rst_n => y_cnt[7].ACLR
rst_n => y_cnt[6].ACLR
rst_n => y_cnt[5].ACLR
rst_n => y_cnt[4].ACLR
rst_n => y_cnt[3].ACLR
rst_n => y_cnt[2].ACLR
rst_n => y_cnt[1].ACLR
rst_n => y_cnt[0].ACLR
rst_n => y_cnt[9].ACLR
rst_n => vga_hsyn.ACLR
rst_n => vga_vsyn.ACLR
rst_n => vga_green.ACLR
rst_n => vga_blue.ACLR
rst_n => vga_red.ACLR
rst_n => clk1.ACLR
clock => clk2.CLK
clock => vga_hsyn.CLK
clock => vga_vsyn.CLK
clock => hsyn~reg0.CLK
clock => vsyn~reg0.CLK
clock => red~reg0.CLK
clock => green~reg0.CLK
clock => blue~reg0.CLK
clock => vga_red.CLK
clock => vga_green.CLK
clock => vga_blue.CLK
clock => clk1.CLK
hsyn <= hsyn~reg0.DB_MAX_OUTPUT_PORT_TYPE
vsyn <= vsyn~reg0.DB_MAX_OUTPUT_PORT_TYPE
red <= red~reg0.DB_MAX_OUTPUT_PORT_TYPE
green <= green~reg0.DB_MAX_OUTPUT_PORT_TYPE
blue <= blue~reg0.DB_MAX_OUTPUT_PORT_TYPE