vga.vo

关于VGA显示的vhdl源代码

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version"

// DATE "01/09/2007 09:55:16"

// 
// Device: Altera EP2C5T144C8 Package TQFP144
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module vga (
	rst_n,
	clock,
	hsyn,
	vsyn,
	red,
	green,
	blue);
input 	rst_n;
input 	clock;
output 	hsyn;
output 	vsyn;
output 	red;
output 	green;
output 	blue;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("vga_v.sdo");
// synopsys translate_on

wire \LessThan3~128 ;
wire vga_red;
wire clk2;
wire \Add2~136 ;
wire \Equal1~86 ;
wire \y_cnt[7]~409 ;
wire \vga_red~302 ;
wire \clk2~2 ;
wire \clk2~clkctrl ;
wire \clock~combout ;
wire \clock~clkctrl ;
wire \Add2~120 ;
wire \rst_n~combout ;
wire \Add2~121 ;
wire \Add2~123 ;
wire \Add2~124 ;
wire \Add2~125 ;
wire \Add2~126 ;
wire \Add2~127 ;
wire \Add2~129 ;
wire \Add2~131 ;
wire \Add2~132 ;
wire \Add2~133 ;
wire \Add2~134 ;
wire \Add2~128 ;
wire \Equal0~78 ;
wire \Add2~130 ;
wire \x_cnt~401 ;
wire \Equal0~76 ;
wire \Equal0~77 ;
wire \Equal0~79 ;
wire \Add2~135 ;
wire \Add2~137 ;
wire \Add2~138 ;
wire \x_cnt~402 ;
wire \LessThan2~134 ;
wire \LessThan2~132 ;
wire \LessThan2~133 ;
wire \LessThan2~135 ;
wire \hsyn~reg0 ;
wire \y_cnt[0]~412 ;
wire \y_cnt[4]~595 ;
wire \y_cnt[5]~596 ;
wire \y_cnt[6]~408 ;
wire \y_cnt[5]~407 ;
wire \y_cnt[6]~598 ;
wire \y_cnt[7]~599 ;
wire \y_cnt[8]~410 ;
wire \Equal1~87 ;
wire \y_cnt[9]~597 ;
wire \y_cnt[0]~591 ;
wire \y_cnt[1]~413 ;
wire \y_cnt[1]~592 ;
wire \y_cnt[2]~593 ;
wire \y_cnt[3]~405 ;
wire \y_cnt[3]~594 ;
wire \y_cnt[4]~406 ;
wire \y_cnt[8]~600 ;
wire \y_cnt[9]~411 ;
wire \Equal1~85 ;
wire \y_cnt[2]~414 ;
wire \LessThan3~127 ;
wire \LessThan3~129 ;
wire \vsyn~reg0 ;
wire \LessThan1~100 ;
wire vga_vsyn;
wire \LessThan0~85 ;
wire vga_hsyn;
wire \red~1 ;
wire \red~reg0 ;
wire \x_cnt~403 ;
wire \vga_blue~245 ;
wire \Add2~122 ;
wire \vga_red~299 ;
wire \vga_red~300 ;
wire \vga_red~301 ;
wire \always10~211 ;
wire \vga_blue~246 ;
wire \vga_green~364 ;
wire \always10~210 ;
wire \always10~212 ;
wire \vga_green~365 ;
wire \vga_green~366 ;
wire vga_green;
wire \green~1 ;
wire \green~reg0 ;
wire \vga_blue~249 ;
wire \vga_blue~247 ;
wire \vga_blue~248 ;
wire \vga_blue~250 ;
wire vga_blue;
wire \blue~1 ;
wire \blue~reg0 ;
wire [9:0] x_cnt;
wire [9:0] y_cnt;


// atom is at LCFF_X22_Y9_N17
cycloneii_lcell_ff \y_cnt[7]~I (
	.clk(\clk2~clkctrl ),
	.datain(\y_cnt[7]~409 ),
	.sdata(gnd),
	.aclr(!\rst_n~combout ),
	.sclr(\Equal0~79 ),
	.sload(gnd),
	.ena(\y_cnt[9]~597 ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(y_cnt[7]));

// atom is at LCCOMB_X21_Y9_N6
cycloneii_lcell_comb \LessThan3~128_I (
// Equation(s):
// \LessThan3~128  = y_cnt[7] # y_cnt[8]

	.dataa(vcc),
	.datab(vcc),
	.datac(y_cnt[7]),
	.datad(y_cnt[8]),
	.cin(gnd),
	.combout(\LessThan3~128 ),
	.cout());
// synopsys translate_off
defparam \LessThan3~128_I .lut_mask = 16'hFFF0;
defparam \LessThan3~128_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCFF_X20_Y9_N3
cycloneii_lcell_ff \vga_red~I (
	.clk(\clock~clkctrl ),
	.datain(\vga_red~302 ),
	.sdata(gnd),
	.aclr(!\rst_n~combout ),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(vga_red));

// atom is at LCFF_X22_Y9_N29
cycloneii_lcell_ff \clk2~I (
	.clk(\clock~clkctrl ),
	.datain(\clk2~2 ),
	.sdata(gnd),
	.aclr(!\rst_n~combout ),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(clk2));

// atom is at LCCOMB_X19_Y9_N22
cycloneii_lcell_comb \Add2~136_I (
// Equation(s):
// \Add2~136  = x_cnt[8] & (\Add2~135  $ GND) # !x_cnt[8] & !\Add2~135  & VCC
// \Add2~137  = CARRY(x_cnt[8] & !\Add2~135 )

	.dataa(x_cnt[8]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.cin(\Add2~135 ),
	.combout(\Add2~136 ),
	.cout(\Add2~137 ));
// synopsys translate_off
defparam \Add2~136_I .lut_mask = 16'hA50A;
defparam \Add2~136_I .sum_lutc_input = "cin";
// synopsys translate_on

// atom is at LCCOMB_X21_Y9_N20
cycloneii_lcell_comb \Equal1~86_I (
// Equation(s):
// \Equal1~86  = y_cnt[0] # y_cnt[2] # !\Equal1~85  # !y_cnt[1]

	.dataa(y_cnt[1]),
	.datab(\Equal1~85 ),
	.datac(y_cnt[0]),
	.datad(y_cnt[2]),
	.cin(gnd),
	.combout(\Equal1~86 ),
	.cout());
// synopsys translate_off
defparam \Equal1~86_I .lut_mask = 16'hFFF7;
defparam \Equal1~86_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X22_Y9_N16
cycloneii_lcell_comb \y_cnt[7]~409_I (
// Equation(s):
// \y_cnt[7]~409  = y_cnt[7] & !\y_cnt[6]~598  # !y_cnt[7] & (\y_cnt[6]~598  # GND)
// \y_cnt[7]~599  = CARRY(!\y_cnt[6]~598  # !y_cnt[7])

	.dataa(y_cnt[7]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.cin(\y_cnt[6]~598 ),
	.combout(\y_cnt[7]~409 ),
	.cout(\y_cnt[7]~599 ));
// synopsys translate_off
defparam \y_cnt[7]~409_I .lut_mask = 16'h5A5F;
defparam \y_cnt[7]~409_I .sum_lutc_input = "cin";
// synopsys translate_on

// atom is at LCCOMB_X20_Y9_N2
cycloneii_lcell_comb \vga_red~302_I (
// Equation(s):
// \vga_red~302  = !x_cnt[9] & x_cnt[8] & \vga_red~300  # !\always10~212 

	.dataa(x_cnt[9]),
	.datab(x_cnt[8]),
	.datac(\vga_red~300 ),
	.datad(\always10~212 ),
	.cin(gnd),
	.combout(\vga_red~302 ),
	.cout());
// synopsys translate_off
defparam \vga_red~302_I .lut_mask = 16'h40FF;
defparam \vga_red~302_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X22_Y9_N28
cycloneii_lcell_comb \clk2~2_I (
// Equation(s):
// \clk2~2  = !clk2

	.dataa(vcc),
	.datab(vcc),
	.datac(clk2),
	.datad(vcc),
	.cin(gnd),
	.combout(\clk2~2 ),
	.cout());
// synopsys translate_off
defparam \clk2~2_I .lut_mask = 16'h0F0F;
defparam \clk2~2_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at CLKCTRL_G4
cycloneii_clkctrl \clk2~clkctrl_I (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,clk2}),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\clk2~clkctrl ));
// synopsys translate_off
defparam \clk2~clkctrl_I .clock_type = "Global Clock";
defparam \clk2~clkctrl_I .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at PIN_88
cycloneii_io \clock~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clock~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(clock));
// synopsys translate_off
defparam \clock~I .input_async_reset = "none";
defparam \clock~I .input_power_up = "low";
defparam \clock~I .input_register_mode = "none";
defparam \clock~I .input_sync_reset = "none";
defparam \clock~I .oe_async_reset = "none";
defparam \clock~I .oe_power_up = "low";
defparam \clock~I .oe_register_mode = "none";
defparam \clock~I .oe_sync_reset = "none";
defparam \clock~I .operation_mode = "input";
defparam \clock~I .output_async_reset = "none";
defparam \clock~I .output_power_up = "low";
defparam \clock~I .output_register_mode = "none";
defparam \clock~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at CLKCTRL_G7
cycloneii_clkctrl \clock~clkctrl_I (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,\clock~combout }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\clock~clkctrl ));
// synopsys translate_off
defparam \clock~clkctrl_I .clock_type = "Global Clock";
defparam \clock~clkctrl_I .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at LCCOMB_X19_Y9_N6
cycloneii_lcell_comb \Add2~120_I (
// Equation(s):
// \Add2~120  = x_cnt[0] $ VCC
// \Add2~121  = CARRY(x_cnt[0])

	.dataa(vcc),
	.datab(x_cnt[0]),
	.datac(vcc),
	.datad(vcc),
	.cin(gnd),
	.combout(\Add2~120 ),
	.cout(\Add2~121 ));
// synopsys translate_off
defparam \Add2~120_I .lut_mask = 16'h33CC;
defparam \Add2~120_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at PIN_97
cycloneii_io \rst_n~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rst_n~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(rst_n));
// synopsys translate_off
defparam \rst_n~I .input_async_reset = "none";
defparam \rst_n~I .input_power_up = "low";
defparam \rst_n~I .input_register_mode = "none";
defparam \rst_n~I .input_sync_reset = "none";
defparam \rst_n~I .oe_async_reset = "none";
defparam \rst_n~I .oe_power_up = "low";
defparam \rst_n~I .oe_register_mode = "none";
defparam \rst_n~I .oe_sync_reset = "none";
defparam \rst_n~I .operation_mode = "input";
defparam \rst_n~I .output_async_reset = "none";
defparam \rst_n~I .output_power_up = "low";
defparam \rst_n~I .output_register_mode = "none";
defparam \rst_n~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCFF_X19_Y9_N7
cycloneii_lcell_ff \x_cnt[0]~I (
	.clk(\clk2~clkctrl ),
	.datain(\Add2~120 ),
	.sdata(gnd),
	.aclr(!\rst_n~combout ),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(x_cnt[0]));

// atom is at LCCOMB_X19_Y9_N8
cycloneii_lcell_comb \Add2~122_I (
// Equation(s):
// \Add2~122  = x_cnt[1] & !\Add2~121  # !x_cnt[1] & (\Add2~121  # GND)
// \Add2~123  = CARRY(!\Add2~121  # !x_cnt[1])

	.dataa(x_cnt[1]),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.cin(\Add2~121 ),
	.combout(\Add2~122 ),
	.cout(\Add2~123 ));
// synopsys translate_off
defparam \Add2~122_I .lut_mask = 16'h5A5F;
defparam \Add2~122_I .sum_lutc_input = "cin";
// synopsys translate_on

// atom is at LCCOMB_X19_Y9_N10
cycloneii_lcell_comb \Add2~124_I (
// Equation(s):
// \Add2~124  = x_cnt[2] & (\Add2~123  $ GND) # !x_cnt[2] & !\Add2~123  & VCC
// \Add2~125  = CARRY(x_cnt[2] & !\Add2~123 )

	.dataa(vcc),
	.datab(x_cnt[2]),
	.datac(vcc),
	.datad(vcc),
	.cin(\Add2~123 ),
	.combout(\Add2~124 ),
	.cout(\Add2~125 ));
// synopsys translate_off
defparam \Add2~124_I .lut_mask = 16'hC30C;
defparam \Add2~124_I .sum_lutc_input = "cin";
// synopsys translate_on

// atom is at LCFF_X19_Y9_N11
cycloneii_lcell_ff \x_cnt[2]~I (
	.clk(\clk2~clkctrl ),
	.datain(\Add2~124 ),
	.sdata(gnd),
	.aclr(!\rst_n~combout ),
	.sclr(gnd),
	.sload(gnd),