vga.tan.rpt

关于VGA显示的vhdl源代码

; N/A                                     ; 219.25 MHz ( period = 4.561 ns )                    ; x_cnt[7] ; y_cnt[9]  ; clock      ; clock    ; None                        ; None                      ; 4.300 ns                ;
; N/A                                     ; 219.25 MHz ( period = 4.561 ns )                    ; x_cnt[7] ; y_cnt[1]  ; clock      ; clock    ; None                        ; None                      ; 4.300 ns                ;
; N/A                                     ; 219.25 MHz ( period = 4.561 ns )                    ; x_cnt[7] ; y_cnt[5]  ; clock      ; clock    ; None                        ; None                      ; 4.300 ns                ;
; N/A                                     ; 219.25 MHz ( period = 4.561 ns )                    ; x_cnt[7] ; y_cnt[0]  ; clock      ; clock    ; None                        ; None                      ; 4.300 ns                ;
; N/A                                     ; 219.25 MHz ( period = 4.561 ns )                    ; x_cnt[7] ; y_cnt[2]  ; clock      ; clock    ; None                        ; None                      ; 4.300 ns                ;
; N/A                                     ; 221.83 MHz ( period = 4.508 ns )                    ; x_cnt[5] ; x_cnt[8]  ; clock      ; clock    ; None                        ; None                      ; 4.245 ns                ;
; N/A                                     ; 222.62 MHz ( period = 4.492 ns )                    ; x_cnt[2] ; x_cnt[8]  ; clock      ; clock    ; None                        ; None                      ; 4.230 ns                ;
; N/A                                     ; 227.22 MHz ( period = 4.401 ns )                    ; x_cnt[3] ; x_cnt[8]  ; clock      ; clock    ; None                        ; None                      ; 4.139 ns                ;
; N/A                                     ; 232.88 MHz ( period = 4.294 ns )                    ; x_cnt[4] ; x_cnt[8]  ; clock      ; clock    ; None                        ; None                      ; 4.032 ns                ;
; N/A                                     ; 235.29 MHz ( period = 4.250 ns )                    ; x_cnt[0] ; x_cnt[9]  ; clock      ; clock    ; None                        ; None                      ; 3.988 ns                ;
; N/A                                     ; 237.25 MHz ( period = 4.215 ns )                    ; y_cnt[1] ; y_cnt[3]  ; clock      ; clock    ; None                        ; None                      ; 3.951 ns                ;
; N/A                                     ; 237.25 MHz ( period = 4.215 ns )                    ; y_cnt[1] ; y_cnt[9]  ; clock      ; clock    ; None                        ; None                      ; 3.951 ns                ;
; N/A                                     ; 237.25 MHz ( period = 4.215 ns )                    ; y_cnt[1] ; y_cnt[1]  ; clock      ; clock    ; None                        ; None                      ; 3.951 ns                ;
; N/A                                     ; 237.25 MHz ( period = 4.215 ns )                    ; y_cnt[1] ; y_cnt[5]  ; clock      ; clock    ; None                        ; None                      ; 3.951 ns                ;
; N/A                                     ; 237.25 MHz ( period = 4.215 ns )                    ; y_cnt[1] ; y_cnt[0]  ; clock      ; clock    ; None                        ; None                      ; 3.951 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;          ;           ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To    ; From Clock ;
+-------+--------------+------------+------------+-------+------------+
; N/A   ; None         ; 9.111 ns   ; green~reg0 ; green ; clock      ;
; N/A   ; None         ; 8.746 ns   ; blue~reg0  ; blue  ; clock      ;
; N/A   ; None         ; 8.653 ns   ; red~reg0   ; red   ; clock      ;
; N/A   ; None         ; 8.208 ns   ; vsyn~reg0  ; vsyn  ; clock      ;
; N/A   ; None         ; 7.991 ns   ; hsyn~reg0  ; hsyn  ; clock      ;
+-------+--------------+------------+------------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Tue Jan 09 09:55:12 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clk2" as buffer
Info: Clock "clock" has Internal fmax of 126.74 MHz between source register "x_cnt[4]" and destination register "vga_blue" (period= 7.89 ns)
    Info: + Longest register to register delay is 3.922 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y9_N15; Fanout = 8; REG Node = 'x_cnt[4]'
        Info: 2: + IC(0.700 ns) + CELL(0.615 ns) = 1.315 ns; Loc. = LCCOMB_X20_Y9_N30; Fanout = 3; COMB Node = 'always10~211'
        Info: 3: + IC(0.594 ns) + CELL(0.370 ns) = 2.279 ns; Loc. = LCCOMB_X21_Y9_N30; Fanout = 1; COMB Node = 'vga_blue~247'
        Info: 4: + IC(0.584 ns) + CELL(0.206 ns) = 3.069 ns; Loc. = LCCOMB_X20_Y9_N16; Fanout = 1; COMB Node = 'vga_blue~248'
        Info: 5: + IC(0.375 ns) + CELL(0.370 ns) = 3.814 ns; Loc. = LCCOMB_X20_Y9_N22; Fanout = 1; COMB Node = 'vga_blue~250'
        Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 3.922 ns; Loc. = LCFF_X20_Y9_N23; Fanout = 1; REG Node = 'vga_blue'
        Info: Total cell delay = 1.669 ns ( 42.55 % )
        Info: Total interconnect delay = 2.253 ns ( 57.45 % )
    Info: - Smallest clock skew is -3.704 ns
        Info: + Shortest clock path from clock "clock" to destination register is 2.764 ns
            Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_88; Fanout = 1; CLK Node = 'clock'
            Info: 2: + IC(0.140 ns) + CELL(0.000 ns) = 1.250 ns; Loc. = CLKCTRL_G7; Fanout = 11; COMB Node = 'clock~clkctrl'
            Info: 3: + IC(0.848 ns) + CELL(0.666 ns) = 2.764 ns; Loc. = LCFF_X20_Y9_N23; Fanout = 1; REG Node = 'vga_blue'
            Info: Total cell delay = 1.776 ns ( 64.25 % )
            Info: Total interconnect delay = 0.988 ns ( 35.75 % )
        Info: - Longest clock path from clock "clock" to source register is 6.468 ns
            Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_88; Fanout = 1; CLK Node = 'clock'
            Info: 2: + IC(0.140 ns) + CELL(0.000 ns) = 1.250 ns; Loc. = CLKCTRL_G7; Fanout = 11; COMB Node = 'clock~clkctrl'
            Info: 3: + IC(0.850 ns) + CELL(0.970 ns) = 3.070 ns; Loc. = LCFF_X22_Y9_N29; Fanout = 2; REG Node = 'clk2'
            Info: 4: + IC(1.884 ns) + CELL(0.000 ns) = 4.954 ns; Loc. = CLKCTRL_G4; Fanout = 20; COMB Node = 'clk2~clkctrl'
            Info: 5: + IC(0.848 ns) + CELL(0.666 ns) = 6.468 ns; Loc. = LCFF_X19_Y9_N15; Fanout = 8; REG Node = 'x_cnt[4]'
            Info: Total cell delay = 2.746 ns ( 42.46 % )
            Info: Total interconnect delay = 3.722 ns ( 57.54 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "clock" to destination pin "green" through register "green~reg0" is 9.111 ns
    Info: + Longest clock path from clock "clock" to source register is 2.765 ns
        Info: 1: + IC(0.000 ns) + CELL(1.110 ns) = 1.110 ns; Loc. = PIN_88; Fanout = 1; CLK Node = 'clock'
        Info: 2: + IC(0.140 ns) + CELL(0.000 ns) = 1.250 ns; Loc. = CLKCTRL_G7; Fanout = 11; COMB Node = 'clock~clkctrl'
        Info: 3: + IC(0.849 ns) + CELL(0.666 ns) = 2.765 ns; Loc. = LCFF_X21_Y9_N25; Fanout = 1; REG Node = 'green~reg0'
        Info: Total cell delay = 1.776 ns ( 64.23 % )
        Info: Total interconnect delay = 0.989 ns ( 35.77 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 6.042 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y9_N25; Fanout = 1; REG Node = 'green~reg0'
        Info: 2: + IC(2.806 ns) + CELL(3.236 ns) = 6.042 ns; Loc. = PIN_136; Fanout = 0; PIN Node = 'green'
        Info: Total cell delay = 3.236 ns ( 53.56 % )
        Info: Total interconnect delay = 2.806 ns ( 46.44 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Tue Jan 09 09:55:12 2007
    Info: Elapsed time: 00:00:01