opencores_can_regs.h

一个用硬件描述语言编写CAN总线控制器的IP

#ifndef __OPENCORES_CAN_REGS_H_
#define __OPENCORES_CAN_REGS_H_

/* register map is for PeliCAN mode - extended */
#define IOADDR_OPENCORES_CAN_MOD(base)                    __IO_CALC_ADDRESS_NATIVE(base,0)
#define IORD_OPENCORES_CAN_MOD(base)                      IORD(base,0)
#define IOWR_OPENCORES_CAN_MOD(base,data)                 IOWR(base,0,data)

#define OPENCORES_CAN_MOD_RM_MSK                          0x01
#define OPENCORES_CAN_MOD_RM_OFST                         0
#define OPENCORES_CAN_MOD_LOM_MSK                         0x02
#define OPENCORES_CAN_MOD_LOM_OFST                        1
#define OPENCORES_CAN_MOD_STM_MSK                         0x04
#define OPENCORES_CAN_MOD_STM_OFST                        2
#define OPENCORES_CAN_MOD_AFM_MSK                         0x08
#define OPENCORES_CAN_MOD_AFM_OFST                        3
#define OPENCORES_CAN_MOD_SM_MSK                          0x10
#define OPENCORES_CAN_MOD_SM_OFST                         4


#define IOADDR_OPENCORES_CAN_CMR(base)                    __IO_CALC_ADDRESS_NATIVE(base,1)
#define IORD_OPENCORES_CAN_CMR(base)                      IORD(base,1)
#define IOWR_OPENCORES_CAN_CMR(base,data)                 IOWR(base,1,data)

#define OPENCORES_CAN_CMR_TR_MSK                          0x01
#define OPENCORES_CAN_CMR_TR_OFST                         0
#define OPENCORES_CAN_CMR_AT_MSK                          0x02
#define OPENCORES_CAN_CMR_AT_OFST                         1
#define OPENCORES_CAN_CMR_RRB_MSK                         0x04
#define OPENCORES_CAN_CMR_RRB_OFST                        2
#define OPENCORES_CAN_CMR_CDO_MSK                         0x08
#define OPENCORES_CAN_CMR_CDO_OFST                        3
#define OPENCORES_CAN_CMR_SRR_MSK                         0x10
#define OPENCORES_CAN_CMR_SRR_OFST                        4


#define IOADDR_OPENCORES_CAN_SR(base)                     __IO_CALC_ADDRESS_NATIVE(base,2)
#define IORD_OPENCORES_CAN_SR(base)                       IORD(base,2)
#define IOWR_OPENCORES_CAN_SR(base)                       IOWR(base,2,write)

#define OPENCORES_CAN_SR_RBS_MSK                          0x01
#define OPENCORES_CAN_SR_RBS_OFST                         0
#define OPENCORES_CAN_SR_DOS_MSK                          0x02
#define OPENCORES_CAN_SR_DOS_OFST                         1
#define OPENCORES_CAN_SR_TBS_MSK                          0x04
#define OPENCORES_CAN_SR_TBS_OFST                         2
#define OPENCORES_CAN_SR_TCS_MSK                          0x08
#define OPENCORES_CAN_SR_TCS_OFST                         3
#define OPENCORES_CAN_SR_RS_MSK                           0x10
#define OPENCORES_CAN_SR_RS_OFST                          4
#define OPENCORES_CAN_SR_TS_MSK                           0x20
#define OPENCORES_CAN_SR_TS_OFST                          5
#define OPENCORES_CAN_SR_ES_MSK                           0x40
#define OPENCORES_CAN_SR_ES_OFST                          6
#define OPENCORES_CAN_SR_BS_MSK                           0x80
#define OPENCORES_CAN_SR_BS_OFST                          7


#define IOADDR_OPENCORES_CAN_IR(base)                     __IO_CALC_ADDRESS_NATIVE(base,3)
#define IORD_OPENCORES_CAN_IR(base)                       IORD(base,3)
#define IOWR_OPENCORES_CAN_IR(base)                       IOWR(base,3,data)

#define OPENCORES_CAN_IR_RI_MSK                           0x01
#define OPENCORES_CAN_IR_RI_OFST                          0
#define OPENCORES_CAN_IR_TI_MSK                           0x02
#define OPENCORES_CAN_IR_TI_OFST                          1
#define OPENCORES_CAN_IR_EI_MSK                           0x04
#define OPENCORES_CAN_IR_EI_OFST                          2
#define OPENCORES_CAN_IR_DOI_MSK                          0x08
#define OPENCORES_CAN_IR_DOI_OFST                         3
#define OPENCORES_CAN_IR_WUI_MSK                          0x10
#define OPENCORES_CAN_IR_WUI_OFST                         4
#define OPENCORES_CAN_IR_EPI_MSK                          0x20
#define OPENCORES_CAN_IR_EPI_OFST                         5
#define OPENCORES_CAN_IR_ALI_MSK                          0x40
#define OPENCORES_CAN_IR_ALI_OFST                         6
#define OPENCORES_CAN_IR_BEI_MSK                          0x80
#define OPENCORES_CAN_IR_BEI_OFST                         7


#define IOADDR_OPENCORES_CAN_IER(base)                    __IO_CALC_ADDRESS_NATIVE(base,4)
#define IORD_OPENCORES_CAN_IER(base)                      IORD(base,4)
#define IOWR_OPENCORES_CAN_IER(base,data)                 IOWR(base,4,data)


#define OPENCORES_CAN_IER_RIE_MSK                         0x01
#define OPENCORES_CAN_IER_RIE_OFST                        0
#define OPENCORES_CAN_IER_TIE_MSK                         0x02
#define OPENCORES_CAN_IER_TIE_OFST                        1
#define OPENCORES_CAN_IER_EIE_MSK                         0x04
#define OPENCORES_CAN_IER_EIE_OFST                        2
#define OPENCORES_CAN_IER_DOIE_MSK                        0x08
#define OPENCORES_CAN_IER_DOIE_OFST                       3
#define OPENCORES_CAN_IER_WUIE_MSK                        0x10
#define OPENCORES_CAN_IER_WUIE_OFST                       4
#define OPENCORES_CAN_IER_EPIE_MSK                        0x20
#define OPENCORES_CAN_IER_EPIE_OFST                       5
#define OPENCORES_CAN_IER_ALIE_MSK                        0x40
#define OPENCORES_CAN_IER_ALIE_OFST                       6
#define OPENCORES_CAN_IER_BEIE_MSK                        0x80
#define OPENCORES_CAN_IER_BEIE_OFST                       7


#define IOADDR_OPENCORES_CAN_BTR0(base)                   __IO_CALC_ADDRESS_NATIVE(base,6)
#define IORD_OPENCORES_CAN_BTR0(base)                     IORD(base,6)
#define IOWR_OPENCORES_CAN_BTR0(base,data)                IOWR(base,6,data)

#define OPENCORES_CAN_BTR0_BRP_MSK                        0x3F
#define OPENCORES_CAN_BTR0_BRP_OFST                       0
#define OPENCORES_CAN_BTR0_SJW_MSK                        0xC0
#define OPENCORES_CAN_BTR0_SJW_OFST                       6


#define IOADDR_OPENCORES_CAN_BTR1(base)                   __IO_CALC_ADDRESS_NATIVE(base,7)
#define IORD_OPENCORES_CAN_BTR1(base)                     IORD(base,7)
#define IOWR_OPENCORES_CAN_BTR1(base,data)                IOWR(base,7,data)

#define OPENCORES_CAN_BTR1_TSEG1_MSK                      0x0F
#define OPENCORES_CAN_BTR1_TSEG1_OFST                     0
#define OPENCORES_CAN_BTR1_TSEG2_MSK                      0x70
#define OPENCORES_CAN_BTR1_TSEG2_OFST                     0
#define OPENCORES_CAN_BTR1_SAM_MSK                        0x80
#define OPENCORES_CAN_BTR1_SAM_OFST                       0


#define IOADDR_OPENCORES_CAN_ALC(base)                    __IO_CALC_ADDRESS_NATIVE(base,11)
#define IORD_OPENCORES_CAN_ALC(base)                      IORD(base,11)

#define OPENCORES_CAN_ALC_ALC_MSK                         0x1F
#define OPENCORES_CAN_ALC_ALC_OFST                        0


#define IOADDR_OPENCORES_CAN_ECC(base)                    __IO_CALC_ADDRESS_NATIVE(base,12)
#define IORD_OPENCORES_CAN_ECC(base)                      IORD(base,12)

#define OPENCORES_CAN_ECC_ECC_MSK                         0xFF
#define OPENCORES_CAN_ECC_ECC_OFST                        0

  
#define IOADDR_OPENCORES_CAN_EWLR(base)                   __IO_CALC_ADDRESS_NATIVE(base,13)
#define IORD_OPENCORES_CAN_EWLR(base)                     IORD(base,13)
#define IOWR_OPENCORES_CAN_EWLR(base,data)                IOWR(base,13,data)

#define OPENCORES_CAN_EWLR_EWLR_MSK                       0xFF
#define OPENCORES_CAN_EWLR_EWLR_OFST                      0


#define IOADDR_OPENCORES_CAN_RXERR(base)                  __IO_CALC_ADDRESS_NATIVE(base,14)
#define IORD_OPENCORES_CAN_RXERR(base)                    IORD(base,14)
#define IOWR_OPENCORES_CAN_RXERR(base,data)               IOWR(base,14,data)

#define OPENCORES_CAN_RXERR_RXERR_MSK                     0xFF
#define OPENCORES_CAN_RXERR_RXERR_OFST                    0


#define IOADDR_OPENCORES_CAN_TXERR(base)                  __IO_CALC_ADDRESS_NATIVE(base,15)
#define IORD_OPENCORES_CAN_TXERR(base)                    IORD(base,15)
#define IOWR_OPENCORES_CAN_TXERR(base,data)               IOWR(base,15,data)

#define OPENCORES_CAN_TXERR_TXERR_MSK                     0xFF
#define OPENCORES_CAN_TXERR_TXERR_OFST                    0


#define IOADDR_OPENCORES_CAN_ACR0(base)                   __IO_CALC_ADDRESS_NATIVE(base,16)
#define IORD_OPENCORES_CAN_ACR0(base)                     IORD(base,16)
#define IOWR_OPENCORES_CAN_ACR0(base,data)                IOWR(base,16,data)

#define OPENCORES_CAN_ACR0_ACR0_MSK                       0xFF
#define OPENCORES_CAN_ACR0_ACR0_OFST                      0


#define IOADDR_OPENCORES_CAN_ACR1(base)                   __IO_CALC_ADDRESS_NATIVE(base,17)
#define IORD_OPENCORES_CAN_ACR1(base)                     IORD(base,17)
#define IOWR_OPENCORES_CAN_ACR1(base,data)                IOWR(base,17,data)

#define OPENCORES_CAN_ACR1_ACR1_MSK                       0xFF
#define OPENCORES_CAN_ACR1_ACR1_OFST                      0

#define IOADDR_OPENCORES_CAN_ACR2(base)                   __IO_CALC_ADDRESS_NATIVE(base,18)
#define IORD_OPENCORES_CAN_ACR2(base)                     IORD(base,18)
#define IOWR_OPENCORES_CAN_ACR2(base,data)                IOWR(base,18,data)

#define OPENCORES_CAN_ACR2_ACR2_MSK                       0xFF
#define OPENCORES_CAN_ACR2_ACR2_OFST                      0


#define IOADDR_OPENCORES_CAN_ACR3(base)                   __IO_CALC_ADDRESS_NATIVE(base,19)
#define IORD_OPENCORES_CAN_ACR3(base)                     IORD(base,19)
#define IOWR_OPENCORES_CAN_ACR3(base,data)                IOWR(base,19,data)

#define OPENCORES_CAN_ACR3_ACR3_MSK                       0xFF
#define OPENCORES_CAN_ACR3_ACR3_OFST                      0


#define IOADDR_OPENCORES_CAN_AMR0(base)                   __IO_CALC_ADDRESS_NATIVE(base,20)
#define IORD_OPENCORES_CAN_AMR0(base)                     IORD(base,20)
#define IOWR_OPENCORES_CAN_AMR0(base,data)                IOWR(base,20,data)

#define OPENCORES_CAN_AMR0_AMR0_MSK                       0xFF
#define OPENCORES_CAN_AMR0_AMR0_OFST                      0


#define IOADDR_OPENCORES_CAN_AMR1(base)                   __IO_CALC_ADDRESS_NATIVE(base,21)
#define IORD_OPENCORES_CAN_AMR1(base)                     IORD(base,21)
#define IOWR_OPENCORES_CAN_AMR1(base,data)                IOWR(base,21,data)

#define OPENCORES_CAN_AMR1_AMR1_MSK                       0xFF
#define OPENCORES_CAN_AMR1_AMR1_OFST                      0


#define IOADDR_OPENCORES_CAN_AMR2(base)                   __IO_CALC_ADDRESS_NATIVE(base,22)
#define IORD_OPENCORES_CAN_AMR2(base)                     IORD(base,22)
#define IOWR_OPENCORES_CAN_AMR2(base,data)                IOWR(base,22,data)

#define OPENCORES_CAN_AMR2_AMR2_MSK                       0xFF
#define OPENCORES_CAN_AMR2_AMR2_OFST                      0


#define IOADDR_OPENCORES_CAN_AMR3(base)                   __IO_CALC_ADDRESS_NATIVE(base,23)
#define IORD_OPENCORES_CAN_AMR3(base)                     IORD(base,23)
#define IOWR_OPENCORES_CAN_AMR3(base,data)                IOWR(base,23,data)

#define OPENCORES_CAN_AMR3_AMR3_MSK                       0xFF
#define OPENCORES_CAN_AMR3_AMR3_OFST                      0


#define IOADDR_OPENCORES_CAN_RMC(base)                    __IO_CALC_ADDRESS_NATIVE(base,29)
#define IORD_OPENCORES_CAN_RMC(base)                      IORD(base,29)
#define IOWR_OPENCORES_CAN_RMC(base,data)                 IOWR(base,29,data)


#define IOADDR_OPENCORES_CAN_CDR(base)                    __IO_CALC_ADDRESS_NATIVE(base,31)
#define IORD_OPENCORES_CAN_CDR(base)                      IORD(base,31)
#define IOWR_OPENCORES_CAN_CDR(base,data)                 IOWR(base,31,data)


#endif  /* __OPENCORES_CAN_REGS_H_ */