class.ptf

一个用硬件描述语言编写CAN总线控制器的IP

#
# This class.ptf file built by Component Editor
# 2005.02.25.11:22:00
#
# DO NOT MODIFY THIS FILE
# If you hand-modify this file you will likely
# interfere with Component Editor's ability to
# read and edit it. And then Component Editor
# will overwrite your changes anyway. So, for
# the very best results, just relax and
# DO NOT MODIFY THIS FILE
#
CLASS opencores_can
{
   MODULE_DEFAULTS 
   {
      class = "opencores_can";
      class_version = "1.0";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
      }
      PORT_WIRING 
      {
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL x101
            {
               name = "OpenCores CAN/opencores_can";
               format = "Divider";
            }
            SIGNAL x102
            {
               name = "av_rst_i";
            }
            SIGNAL x103
            {
               name = "av_cs_i";
            }
            SIGNAL x104
            {
               name = "av_wr_i";
            }
            SIGNAL x105
            {
               name = "av_dat_i";
               radix = "hexadecimal";
            }
            SIGNAL x106
            {
               name = "av_adr_i";
               radix = "hexadecimal";
            }
            SIGNAL x107
            {
               name = "clk_i";
            }
            SIGNAL x108
            {
               name = "rx_i";
            }
            SIGNAL x109
            {
               name = "av_dat_o";
               radix = "hexadecimal";
            }
            SIGNAL x110
            {
               name = "tx_o";
            }
            SIGNAL x111
            {
               name = "bus_off_on";
            }
            SIGNAL x112
            {
               name = "irq_on";
            }
            SIGNAL x113
            {
               name = "clkout_o";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         hdl_parameters 
         {
            tp = "1";
         }
      }
      SLAVE opencores_can
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Width = "8";
            Address_Alignment = "native";
            Data_Width = "8";
            Has_Base_Address = "1";
            Has_IRQ = "1";
            Setup_Time = "0cycles";
            Hold_Time = "0cycles";
            Read_Wait_States = "1cycles";
            Write_Wait_States = "0cycles";
            Read_Latency = "0";
            Max_Pending_Read_Transactions = "1";
            Is_Printable_Device = "0";
            Is_Memory_Device = "0";
         }
         PORT_WIRING 
         {
            PORT av_rst_i
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "reset";
            }
            PORT av_cs_i
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "chipselect";
            }
            PORT av_wr_i
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "write";
            }
            PORT av_dat_i
            {
               width = "8";
               width_expression = "";
               direction = "input";
               type = "writedata";
            }
            PORT av_adr_i
            {
               width = "8";
               width_expression = "";
               direction = "input";
               type = "address";
            }
            PORT clk_i
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "clk";
            }
            PORT rx_i
            {
               width = "1";
               width_expression = "";
               direction = "input";
               type = "export";
            }
            PORT av_dat_o
            {
               width = "8";
               width_expression = "";
               direction = "output";
               type = "readdata";
            }
            PORT tx_o
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
            }
            PORT bus_off_on
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
            }
            PORT irq_on
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "irq";
            }
            PORT clkout_o
            {
               width = "1";
               width_expression = "";
               direction = "output";
               type = "export";
            }
         }
         COMPONENT_BUILDER 
         {
            AVS_SETTINGS 
            {
               Setup_Value = "0";
               Read_Wait_Value = "1";
               Write_Wait_Value = "0";
               Hold_Value = "0";
               Timing_Units = "cycles";
               Read_Latency_Value = "0";
               Max_Pending_Read_Transactions_Value = "1";
               Address_Alignment = "native";
               Is_Printable_Device = "0";
               Is_Memory_Device = "0";
               external_wait = "0";
            }
         }
      }
   }
   USER_INTERFACE 
   {
      USER_LABELS 
      {
         name = "OpenCores CAN";
         technology = "User Logic";
      }
      WIZARD_UI the_wizard_ui
      {
         title = "OpenCores CAN - {{ $MOD }}";
         CONTEXT 
         {
            H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
            M = "";
            SBI_opencores_can = "SLAVE opencores_can/SYSTEM_BUILDER_INFO";
         }
         PAGES main
         {
            PAGE 1
            {
               align = "left";
               title = "<b>OpenCores CAN</b> Settings";
               layout = "vertical";
               TEXT 
               {
                  title = "Built on: 2005.02.25.11:22:00";
               }
               TEXT 
               {
                  title = "Class name: opencores_can";
               }
               TEXT 
               {
                  title = "Component name: OpenCores CAN";
               }
               TEXT 
               {
                  title = "Component Group: User Logic";
               }
               GROUP parameters
               {
                  title = "Parameters";
                  layout = "form";
                  align = "left";
                  EDIT e1
                  {
                     editable = "1";
                     title = "Tp:";
                     tooltip = "";
                     DATA 
                     {
                        $H/tp = "$";
                     }
                  }
               }
            }
         }
      }
   }
   CB_GENERATOR 
   {
      top_module_name = "can_top.v:can_top";
      emit_system_h = "0";
      HDL_FILES 
      {
         FILE 
         {
            filepath = "hdl/can_acf.v";
            use_in_simulation = "1";
            use_in_synthesis = "1";
         }
         FILE 
         {
            filepath = "hdl/can_bsp.v";
            use_in_simulation = "1";
            use_in_synthesis = "1";
         }
         FILE 
         {
            filepath = "hdl/can_btl.v";
            use_in_simulation = "1";
            use_in_synthesis = "1";
         }
         FILE 
         {
            filepath = "hdl/can_crc.v";
            use_in_simulation = "1";
            use_in_synthesis = "1";
         }
         FILE 
         {
            filepath = "hdl/can_defines.v";
            use_in_simulation = "1";
            use_in_synthesis = "1";
         }
         FILE 
         {
            filepath = "hdl/can_fifo.v";
            use_in_simulation = "1";
            use_in_synthesis = "1";
         }
         FILE 
         {
            filepath = "hdl/can_ibo.v";
            use_in_simulation = "1";
            use_in_synthesis = "1";
         }
         FILE 
         {
            filepath = "hdl/can_register.v";
            use_in_simulation = "1";
            use_in_synthesis = "1";
         }
         FILE 
         {
            filepath = "hdl/can_register_asyn.v";
            use_in_simulation = "1";
            use_in_synthesis = "1";
         }
         FILE 
         {
            filepath = "hdl/can_register_asyn_syn.v";
            use_in_simulation = "1";
            use_in_synthesis = "1";