top.vhd.bak

来自「应用VHDL编写程序」· BAK 代码 · 共 53 行

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.commonConstants.all;

entity top is port(
	clk, reset: in STD_LOGIC;
	mem_enX, mem_rwX : out std_logic;
	aBusX : out std_logic_vector(adrLength-1 downto 0);
	dBusX : out std_logic_vector(wordSize-1 downto 0);
	pcX, iarX : out std_logic_vector(adrLength-1 downto 0);
	iregX, accX, aluX, RiX : out std_logic_vector(wordSize-1 downto 0);
	cyX : out std_logic_vector(0 downto 0);
	cyaccX : out std_logic_vector(wordSize downto 0));
end top;

architecture topArch of top is

component ram port (
        reset, en, r_w: in STD_LOGIC;
        aBus: in STD_LOGIC_VECTOR(adrLength-1 downto 0);
        dBus: inout STD_LOGIC_VECTOR(wordSize-1 downto 0));
end component;

component cpu port (
    	clk, reset:	in  STD_LOGIC;
    	m_en, m_rw: out STD_LOGIC;    	
	aBus:	out STD_LOGIC_VECTOR(adrLength-1 downto 0);
	dBus:	inout STD_LOGIC_VECTOR(wordSize-1 downto 0);
	pcX, iarX : out std_logic_vector(wordSize-1 downto 0);
	iregX, accX, aluX, RiX : out std_logic_vector(wordSize-1 downto 0);
	cyX : out std_logic_vector(0 downto 0);
	cyaccX : out std_logic_vector(wordSize downto 0));
end component;

signal mem_en, mem_rw: STD_LOGIC;
signal aBus, dBus: STD_LOGIC_VECTOR(31 downto 0);
signal pc, ireg, iar, acc, alu, Ri, cy, cyacc : std_logic_vector(31 downto 0);
signal cy : std_logic_vector(0 downto 0);
signal	cyacc : std_logic_vector(32 downto 0);

begin
	ramC: ram port map(reset, mem_en, mem_rw, aBus, dBus);
	cpuC: cpu port map(clk, reset, mem_en, mem_rw, aBus, dBus,
			pc, iar, ireg, acc, alu, Ri, cy, cyacc);
	mem_enX <= mem_en; mem_rwX <= mem_rw;
	aBusX <= aBus; dBusX <= dBus;
	pcX <= pc; iregX <= ireg; iarX <= iar; 
	accX <= acc; aluX <= alu; RiX <= Ri; 
	cyX <= cy; cyacc <= cyacc;
end topArch;