ram.vhd.bak

应用VHDL编写程序

package commonConstants is
	constant wordSize: integer := 32;
	constant adrLength: integer := 32;
end package commonConstants;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.commonConstants.all;

entity ram is port (
        reset, en, r_w: in STD_LOGIC;
        aBus: in STD_LOGIC_VECTOR(adrLength-1 downto 0);
        dBus: inout STD_LOGIC_VECTOR(wordSize-1 downto 0));
end ram;

architecture ramArch of ram is
constant resAdrLength: integer := 6; -- address length restricted within architecture
constant memSize: integer := 2**resAdrLength;
type ram_typ is array(0 to memSize-1) of STD_LOGIC_VECTOR(wordSize-1 downto 0);
signal ram: ram_typ;
begin
	process(reset, en, r_w, aBus, dBus) begin
	  	if reset = '1' then
		      	-- basic instruction check
	        	  ram(0)   <= x"e8000020"; -- jmp
              ram(1)   <= x"00000001";
              --example
		        ram(2)   <= x"fffffffd";
		        ram(3)   <= x"00000001";
		        ram(4)   <= x"00000001";
		        ram(5)   <= x"ffffffff";
		        ram(6)   <= x"ffffffff";
		        ram(7)   <= x"ffffffff";
		        ----
		        ram(32)   <= x"d0000003";--lda
		        ram(33)   <= x"b8000000";--mov
		        ram(34)   <= x"d0000005";--lda
		        ram(35)   <= x"b0000000";--add
		        ram(36)   <= x"d8000007";--sta
		        ram(37)   <= x"d0000002";--lda
		        ram(38)   <= x"b8000000";--mov
		        ram(39)   <= x"d0000004";--lda
		        ram(40)   <= x"e000002c";--jc
		        ram(41)   <= x"b0000000";--add
		        ram(42)   <= x"d8000006";--sta
		        ram(43)   <= x"e800002e";--jmp
		        ram(44)   <= x"b0000000";--add
		        ram(45)   <= x"f0000000";--inc
		        ram(46)   <= x"d8000006";--sta
		        ram(47)   <= x"00000000";--halt
		        
		elsif en = '1' and r_w = '0' then
	  		ram(conv_integer(unsigned(aBus(resAdrLength-1 downto 0)))) <= dBus;
		end if;
	end process;
	dBus <= ram(conv_integer(unsigned(aBus(resAdrLength-1 downto 0))))
  			when reset = '0' and en = '1' and r_w = '1' else
			(dbus'range => 'Z');
end ramArch;