cpld-clock.vhd

VHDL语言编写的时钟显示代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 entity clock is port
( inclk: in std_logic;
  keyclr:in std_logic;
        oe1  :out std_logic;
        oe2  :out std_logic;
        dir1 :out std_logic;
        dir2 :out std_logic; 
  outseg:out std_logic_vector(7 downto 0);
  outbit:out std_logic_vector(7 downto 0));
end clock;
 Architecture a_counter of clock is
   signal ma,mb,mc,md,me,mf,mg,mh,mseg:std_logic_vector(3 downto 0);
   signal lm ,hm: std_logic_vector(16 downto 0);
   signal fpa,fpb: std_logic;
   signal st: std_logic_vector(2 downto 0);
  begin
 process(inclk)
    begin
      if (inclk'event and inclk='1') then
         if lm=24999 then 
            lm<="00000000000000000";fpa<=not fpa;
         else
            lm<=lm+1;
         end if;
       end if;
  end process;

  process(fpa)
     begin
       if (fpa'event and fpa='1') then
          if hm=499 then 
             hm<="00000000000000000";fpb<=not fpb;
          else
             hm<=hm+1;
          end if;
        end if;
   end process;

process(fpb)
    begin
       if (keyclr='0') then
           ma<="0000";  mb<="0000"; mc<="0000";
           md<="0000";  me<="0000"; mf<="0000";
       else if (fpb'event and fpb='1') then
                mg<="1111";
                mh<="1111";
                if ma=9 then
                   ma<="0000";
                   if mb=5 then
                      mb<="0000";
                      if mc=9 then
                         mc<="0000";
                         if md=5 then
                            md<="0000";
                            if(me=3 and mf=2)then
                               me<="0000";mf<="0000";
                            else
                               if me=9 then
                                  mf<=mf+1; me<="0000";
                               else
                                  me<=me+1;
                               end if;
                             end if; 
                          else
                             md<=md+1;
                          end if;
                       else
                         mc<=mc+1;
                       end if;
                    else
                      mb<=mb+1;
                    end if;
                 else
                   ma<=ma+1;
                 end if;
           end if;
       end if;
    end process;

process (fpa)
  begin 
    if(fpa'event and fpa='1') then
       st<=st+1;
    end if;
end process;

process (st)
  begin 
    case st is
       when "000" =>
            mseg<=ma;
            outbit<="11111110";
       when "001"=>
            mseg<=mb;
            outbit<="11111101";
       when "010"=>
            mseg<=mg;                               
            outbit<="11111011";
       when "011"=>
            mseg<=mc;
            outbit<="11110111";
       when "100"=>
            mseg<=md;
            outbit<="11101111";
       when "101"=>
            mseg<=mh;   
            outbit<="11011111";
       when "110"=>
            mseg<=me;
            outbit<="10111111";
       when "111"=>
            mseg<=mf;
            outbit<="01111111";
       when others=>outbit<="ZZZZZZZZ";      
    end case;
end process;

Process(mc)
  begin
    case mseg  is
       when "0001"=>   outseg<="00110000";      --1
       when "0010"=>   outseg<="01101101";      --2
       when "0011"=>   outseg<="01111001";      --3
       when "0100"=>   outseg<="00110011";      --4
       when "0101"=>   outseg<="01011011";      --5
       when "0110"=>   outseg<="01011111";      --6
       when "0111"=>   outseg<="01110000";      --7
       when "1000"=>   outseg<="01111111";      --8
       when "1001"=>   outseg<="01111011";      --9
       when "1010"=>   outseg<="01110111";      --A
       when "1011"=>   outseg<="00011111";      --b
       when "1100"=>   outseg<="01001110";      --C
       when "1101"=>   outseg<="00111101";      --d
       when "1110"=>   outseg<="01001111";      --E
       when "1111"=>   outseg<="00000001";      --"-"
       when others=>   outseg<="01111110";      --0
  end case;
end process;

   oe1<='0';
   dir1<='1';
   oe2<='0';
   dir2<='1';
  
end a_counter;