sdcard_spi.vhd

这是一个SD卡的TESTBENCH,源码中有如何产生一个特定的命令序列的样例。支持产生任何的SD卡交互过程中用到的命令序列。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sdcard_spi is
	generic(
		write_block_length:integer:=512;
		sd_card_size:integer:=4*1024
	);
	port(
		res:in std_logic; --for test only
		cs:in std_logic;
		clk:in std_logic;
		di:in std_logic;
--		test_is_cmd:out std_logic;
--		test_is_start_block:out std_logic;
--		test_din_8:out std_logic_vector(47 downto 0);
--		test_crc_result_cmd:out std_logic;
--		test_crc_result_data:out std_logic;
		do:out std_logic
	);
end entity;

architecture behave of sdcard_spi is

component CRC16Generator
	port(
		RST:in std_logic;
		TestData:in std_logic;
		Clock:in std_logic;
		Hold:in std_logic;
		CRC:out std_logic_vector(15 downto 0)
	); 
end component;

component CRC7Generator
	port(
		RST:in std_logic;
		TestData:in std_logic;
		Clock:in std_logic;
		Hold:in std_logic;
		CRC:out std_logic_vector(6 downto 0)
	);
end component;

component csdcid_rom
	port(
		address:in std_logic_vector(4 downto 0);
		clock:in std_logic;
		q:out std_logic_vector(7 downto 0)
	);
end component;

--globally used
constant idle_output:std_logic_vector(7 downto 0):="11111111";
constant inactive_state:std_logic_vector(10 downto 0) :="00000000001";
constant standby_state:std_logic_vector(10 downto 0)  :="00000000010";
constant working_state:std_logic_vector(10 downto 0)  :="00000000100";
constant sendr2_state:std_logic_vector(10 downto 0)   :="00000001000";
constant sendr3_state:std_logic_vector(10 downto 0)   :="00000010000";
constant toread_state:std_logic_vector(10 downto 0)   :="00000100000";
constant reading_state:std_logic_vector(10 downto 0)  :="00001000000";
constant towrite_state:std_logic_vector(10 downto 0)  :="00010000000";
constant buffering_state:std_logic_vector(10 downto 0):="00100000000";
constant writing_state:std_logic_vector(10 downto 0)  :="01000000000";
constant erasing_state:std_logic_vector(10 downto 0)  :="10000000000";

signal current_state:std_logic_vector(10 downto 0):=inactive_state;
signal cur_block_len:std_logic_vector(8 downto 0);  --the current size of block length
signal CRC_enable:std_logic:='0';

--initial part
signal din_buf:std_logic_vector(47 downto 0):=(others=>'1');  --last 48 bits to the main process
signal d_in_cmd:std_logic;
signal in_cmd:std_logic;  --whether inside a cmd
signal go_start_cmd:std_logic;
signal cnt_8:std_logic_vector(2 downto 0); --cnt form 0 to 7
signal cnt_cmd:std_logic_vector(7 downto 0);  --cnt_cmd form 0 to 48 maximal
signal cnt_data:std_logic_vector(9 downto 0);
signal crc7_res:std_logic;
signal crc:std_logic_vector(6 downto 0);
signal crc_data:std_logic_vector(15 downto 0);
signal d_crc_result_cmd:std_logic;
signal crc16_res:std_logic;
signal go_start_data:std_logic;
signal in_data:std_logic;  --whether inside a data block
signal end_data:std_logic;

signal is_cmd:std_logic; --whether the din_8 is representing a cmd
signal is_start_block:std_logic; --whether the din_8 is representing a start block token
signal data_ended:std_logic;  --whether a data block is about to end
signal crc_result_cmd:std_logic:='0';  --represent the condition of last cmd crc check
signal crc_result_data:std_logic:='0';  --represent the conditon of last data block crc check
signal din_8:std_logic_vector(47 downto 0):=(others=>'1'); --data given to main process
signal clk0:std_logic;  --clock for byte process

--main part
signal next_state:std_logic_vector(10 downto 0);
signal last_is_cmd55:std_logic;
signal terminated:std_logic;
signal readed:std_logic;
signal writed:std_logic;
signal reading_finished:std_logic;
signal writing_finished:std_logic;
signal erasing_finished:std_logic;
signal sendr3_finished:std_logic;

signal dout_8:std_logic_vector(7 downto 0):=(others=>'1');

begin
--intialization part-----
	process(clk, cs)
	begin
		if cs='1' then
			din_buf<=(others=>'1');
		elsif clk='1' and clk'event then
			din_buf(47 downto 1)<=din_buf(46 downto 0);
			din_buf(0)<=di;
		end if;
	end process;
	
	process(clk, cs)
	begin
		if cs='1' then
			cnt_8<=(others=>'0');
		elsif clk='1' and clk'event then
			cnt_8<=cnt_8+1;
		end if;
	end process;
	

end architecture;