16cunter.vhd

来自「这是一个SD卡的TESTBENCH,源码中有如何产生一个特定的命令序列的样例。支」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity Counter16 is 
	port(Clock:in std_logic:='0';
	Count:out std_logic_vector(3 downto 0):="0110");
end entity;
architecture Counter16Arc of Counter16 is
--signal CountVar:std_logic_vector(3 downto 0):="0110"; 
signal CountTest:integer:=0;
begin
	MainProcess:
	process(Clock)
	begin
		variable CountVar:std_logic_vector(3 downto 0);
		
		if Clock='1' and Clock'event then --and Clock'event then 
		--	Count<="1111";
		--else
			--Count<="0000";
			if CountTest+1<16 then
				CountTest<=CountTest+1;
			else
				CountTest<=0;
			end if;
			if CountVar+1<16 then 
				CountVar:=CountVar+1;
			else
				CountVar:="0000";
			end if;
		end if;
		Count<=CountVar;
	end process;
end architecture;