chuan_to_bing.txt

16位A/D转换程序

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY chuan_to_bing IS
	PORT(clk	   : IN std_logic;	
		 addr	   : IN std_logic_vector(15 DOWNTO 0);			
         chuan_in  : IN std_logic;
		 able	   : OUT std_logic;
		 bing_out  : OUT std_logic_vector(15 DOWNTO 0));
END;

ARCHITECTURE ad OF chuan_to_bing IS
	SIGNAL addrs :std_logic_vector(15 DOWNTO 0);
	SIGNAL chuan :std_logic;
	SIGNAL bing  :std_logic_vector(15 DOWNTO 0);
	SIGNAL current_state: INTEGER RANGE 0 TO 15 ;

BEGIN
	PROCESS(clk)
		VARIABLE enable:std_logic;
	BEGIN
		addrs<=addr;
		IF addrs="1000000000000000" THEN 
			enable:='1';
		ELSE enable:='0';
		END IF;	
		IF (clk'event AND clk='1')  THEN
			IF enable='1' THEN			
				chuan<= chuan_in;	
			CASE current_state IS
				WHEN 0 => bing(0)<=chuan;
						  current_state <= 1;
				WHEN 1 => bing(1)<=chuan;
						  current_state <= 2;
				WHEN 2 => bing(2)<=chuan;
						  current_state <= 3;
				WHEN 3 => bing(3)<=chuan;
						  current_state <= 4;
				WHEN 4 => bing(4)<=chuan;
						  current_state <= 5;
				WHEN 5 => bing(5)<=chuan;
						  current_state <= 6;
				WHEN 6 => bing(6)<=chuan;
						  current_state <= 7;
				WHEN 7 => bing(7)<=chuan;
						  current_state <= 8;
				WHEN 8 => bing(8)<=chuan;
						  current_state <= 9;
				WHEN 9 => bing(9)<=chuan;
						  current_state <= 10;
				WHEN 10 => bing(10)<=chuan;
						  current_state <= 11;
				WHEN 11 => bing(11)<=chuan;
						  current_state <= 12;
				WHEN 12 => bing(12)<=chuan;
						  current_state <= 13;
				WHEN 13 => bing(13)<=chuan;
						  current_state <= 14;
				WHEN 14 => bing(14)<=chuan;
						  current_state <= 15;
				WHEN 15 => bing(15)<=chuan;
						current_state <= 0;		
			END CASE;
			END IF;
		END IF;
		IF (clk'event AND clk='1')  THEN
			IF (enable='0') THEN
				bing_out<=bing;
			END IF;
		END IF;
	able<=enable;
	END PROCESS;
END;