📄 watch.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "cp2 register numlet\[0\] register num\[3\] 71.43 MHz 14.0 ns Internal " "Info: Clock cp2 has Internal fmax of 71.43 MHz between source register numlet\[0\] and destination register num\[3\] (period= 14.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns numlet\[0\] 1 REG LC58 35 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC58; Fanout = 35; REG Node = 'numlet\[0\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "" { numlet[0] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns num~4311 2 COMB LC65 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC65; Fanout = 1; COMB Node = 'num~4311'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { numlet[0] num~4311 } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns num\[3\] 3 REG LC66 23 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC66; Fanout = 23; REG Node = 'num\[3\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "1.000 ns" { num~4311 num[3] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 77.78 % " "Info: Total cell delay = 7.000 ns ( 77.78 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 22.22 % " "Info: Total interconnect delay = 2.000 ns ( 22.22 % )" { } { } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "9.000 ns" { numlet[0] num~4311 num[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp2 destination 12.000 ns + Shortest register " "Info: + Shortest clock path from clock cp2 to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns cp2 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'cp2'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "" { cp2 } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns count\[10\] 2 REG LC52 24 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC52; Fanout = 24; REG Node = 'count\[10\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "1.000 ns" { cp2 count[10] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 29 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns num\[3\] 3 REG LC66 23 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC66; Fanout = 23; REG Node = 'num\[3\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { count[10] num[3] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" { } { } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] num[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp2 source 12.000 ns - Longest register " "Info: - Longest clock path from clock cp2 to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns cp2 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'cp2'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "" { cp2 } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns count\[10\] 2 REG LC52 24 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC52; Fanout = 24; REG Node = 'count\[10\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "1.000 ns" { cp2 count[10] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 29 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns numlet\[0\] 3 REG LC58 35 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC58; Fanout = 35; REG Node = 'numlet\[0\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { count[10] numlet[0] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" { } { } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] numlet[0] } "NODE_NAME" } } } } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] num[3] } "NODE_NAME" } } } { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] numlet[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 64 -1 0 } } } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "9.000 ns" { numlet[0] num~4311 num[3] } "NODE_NAME" } } } { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] num[3] } "NODE_NAME" } } } { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] numlet[0] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "num1\[0\] beginstop cp2 2.000 ns register " "Info: tsu for register num1\[0\] (data pin = beginstop, clock pin = cp2) is 2.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns beginstop 1 PIN PIN_84 42 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_84; Fanout = 42; PIN Node = 'beginstop'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "" { beginstop } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns num1\[0\] 2 REG LC69 43 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC69; Fanout = 43; REG Node = 'num1\[0\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "7.000 ns" { beginstop num1[0] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 45 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" { } { } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "10.000 ns" { beginstop num1[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 45 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp2 destination 12.000 ns - Shortest register " "Info: - Shortest clock path from clock cp2 to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns cp2 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'cp2'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "" { cp2 } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns cp1 2 REG LC60 25 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC60; Fanout = 25; REG Node = 'cp1'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "1.000 ns" { cp2 cp1 } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 29 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns num1\[0\] 3 REG LC69 43 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC69; Fanout = 43; REG Node = 'num1\[0\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { cp1 num1[0] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 45 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" { } { } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 cp1 num1[0] } "NODE_NAME" } } } } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "10.000 ns" { beginstop num1[0] } "NODE_NAME" } } } { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 cp1 num1[0] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "cp2 seg\[1\] num\[0\] 44.000 ns register " "Info: tco from clock cp2 to destination pin seg\[1\] through register num\[0\] is 44.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp2 source 12.000 ns + Longest register " "Info: + Longest clock path from clock cp2 to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns cp2 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'cp2'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "" { cp2 } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns count\[10\] 2 REG LC52 24 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC52; Fanout = 24; REG Node = 'count\[10\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "1.000 ns" { cp2 count[10] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 29 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns num\[0\] 3 REG LC82 26 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC82; Fanout = 26; REG Node = 'num\[0\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { count[10] num[0] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" { } { } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] num[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "31.000 ns + Longest register pin " "Info: + Longest register to pin delay is 31.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns num\[0\] 1 REG LC82 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC82; Fanout = 26; REG Node = 'num\[0\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "" { num[0] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns process2~458 2 COMB LC93 1 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC93; Fanout = 1; COMB Node = 'process2~458'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "9.000 ns" { num[0] process2~458 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 18.000 ns segsig\[1\]\$d_and~74 3 COMB LC107 2 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 18.000 ns; Loc. = LC107; Fanout = 2; COMB Node = 'segsig\[1\]\$d_and~74'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "9.000 ns" { process2~458 segsig[1]$d_and~74 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 27.000 ns segsig\[1\]~90 4 COMB LC8 3 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 27.000 ns; Loc. = LC8; Fanout = 3; COMB Node = 'segsig\[1\]~90'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "9.000 ns" { segsig[1]$d_and~74 segsig[1]~90 } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 62 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 31.000 ns seg\[1\] 5 PIN PIN_9 0 " "Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 31.000 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'seg\[1\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "4.000 ns" { segsig[1]~90 seg[1] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "25.000 ns 80.65 % " "Info: Total cell delay = 25.000 ns ( 80.65 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 19.35 % " "Info: Total interconnect delay = 6.000 ns ( 19.35 % )" { } { } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "31.000 ns" { num[0] process2~458 segsig[1]$d_and~74 segsig[1]~90 seg[1] } "NODE_NAME" } } } } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] num[0] } "NODE_NAME" } } } { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "31.000 ns" { num[0] process2~458 segsig[1]$d_and~74 segsig[1]~90 seg[1] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TH_RESULT" "num1\[0\] beginstop cp2 6.000 ns register " "Info: th for register num1\[0\] (data pin = beginstop, clock pin = cp2) is 6.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp2 destination 12.000 ns + Longest register " "Info: + Longest clock path from clock cp2 to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns cp2 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'cp2'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "" { cp2 } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns cp1 2 REG LC60 25 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC60; Fanout = 25; REG Node = 'cp1'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "1.000 ns" { cp2 cp1 } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 29 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns num1\[0\] 3 REG LC69 43 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC69; Fanout = 43; REG Node = 'num1\[0\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { cp1 num1[0] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 45 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" { } { } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 cp1 num1[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" { } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 45 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns beginstop 1 PIN PIN_84 42 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_84; Fanout = 42; PIN Node = 'beginstop'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "" { beginstop } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(6.000 ns) 10.000 ns num1\[0\] 2 REG LC69 43 " "Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC69; Fanout = 43; REG Node = 'num1\[0\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "7.000 ns" { beginstop num1[0] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 45 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns 90.00 % " "Info: Total cell delay = 9.000 ns ( 90.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 10.00 % " "Info: Total interconnect delay = 1.000 ns ( 10.00 % )" { } { } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "10.000 ns" { beginstop num1[0] } "NODE_NAME" } } } } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 cp1 num1[0] } "NODE_NAME" } } } { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "10.000 ns" { beginstop num1[0] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "cp2 sel\[6\] selsig\[6\] 17.000 ns register " "Info: Minimum tco from clock cp2 to destination pin sel\[6\] through register selsig\[6\] is 17.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp2 source 12.000 ns + Shortest register " "Info: + Shortest clock path from clock cp2 to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns cp2 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'cp2'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "" { cp2 } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns count\[10\] 2 REG LC52 24 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC52; Fanout = 24; REG Node = 'count\[10\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "1.000 ns" { cp2 count[10] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 29 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns selsig\[6\] 3 REG LC59 2 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC59; Fanout = 2; REG Node = 'selsig\[6\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "8.000 ns" { count[10] selsig[6] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" { } { } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] selsig[6] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns selsig\[6\] 1 REG LC59 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC59; Fanout = 2; REG Node = 'selsig\[6\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "" { selsig[6] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 64 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns sel\[6\] 2 PIN PIN_35 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_35; Fanout = 0; PIN Node = 'sel\[6\]'" { } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "4.000 ns" { selsig[6] sel[6] } "NODE_NAME" } } } { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 6 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" { } { } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "4.000 ns" { selsig[6] sel[6] } "NODE_NAME" } } } } 0} } { { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "12.000 ns" { cp2 count[10] selsig[6] } "NODE_NAME" } } } { "D:/yw/db/watch_cmp.qrpt" "" "" { Report "D:/yw/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "D:/yw/db/watch.quartus_db" { Floorplan "" "" "4.000 ns" { selsig[6] sel[6] } "NODE_NAME" } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 23 14:06:06 2006 " "Info: Processing ended: Mon Oct 23 14:06:06 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0} } { } 0}
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