watch.map.qmsg

自己编的走马灯程序 用了就知道 太好使了 真的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Oct 23 14:05:51 2006 " "Info: Processing started: Mon Oct 23 14:05:51 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off watch -c watch " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off watch -c watch" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "watch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file watch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 watch-behave " "Info: Found design unit 1: watch-behave" {  } { { "D:/yw/watch.vhd" "watch-behave" "" { Text "D:/yw/watch.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 watch " "Info: Found entity 1: watch" {  } { { "D:/yw/watch.vhd" "watch" "" { Text "D:/yw/watch.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count watch.vhd(35) " "Warning: VHDL Process Statement warning at watch.vhd(35): signal count is in statement, but is not in sensitivity list" {  } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 35 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset watch.vhd(39) " "Warning: VHDL Process Statement warning at watch.vhd(39): signal reset is in statement, but is not in sensitivity list" {  } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 39 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(80) " "Warning: VHDL Process Statement warning at watch.vhd(80): signal num is in statement, but is not in sensitivity list" {  } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 80 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(82) " "Warning: VHDL Process Statement warning at watch.vhd(82): signal num is in statement, but is not in sensitivity list" {  } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 82 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(84) " "Warning: VHDL Process Statement warning at watch.vhd(84): signal num is in statement, but is not in sensitivity list" {  } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 84 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(86) " "Warning: VHDL Process Statement warning at watch.vhd(86): signal num is in statement, but is not in sensitivity list" {  } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 86 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(88) " "Warning: VHDL Process Statement warning at watch.vhd(88): signal num is in statement, but is not in sensitivity list" {  } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 88 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(90) " "Warning: VHDL Process Statement warning at watch.vhd(90): signal num is in statement, but is not in sensitivity list" {  } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 90 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(92) " "Warning: VHDL Process Statement warning at watch.vhd(92): signal num is in statement, but is not in sensitivity list" {  } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 92 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(94) " "Warning: VHDL Process Statement warning at watch.vhd(94): signal num is in statement, but is not in sensitivity list" {  } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 94 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(96) " "Warning: VHDL Process Statement warning at watch.vhd(96): signal num is in statement, but is not in sensitivity list" {  } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 96 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "num watch.vhd(98) " "Warning: VHDL Process Statement warning at watch.vhd(98): signal num is in statement, but is not in sensitivity list" {  } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 98 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "segsig watch.vhd(62) " "Warning: VHDL Process Statement warning at watch.vhd(62): signal or variable segsig may not be assigned a new value in every possible path through the Process Statement. Signal or variable segsig holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "D:/yw/watch.vhd" "" "" { Text "D:/yw/watch.vhd" 62 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" "lpm_add_sub" "" { Text "c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "c:/altera/quartus41/libraries/megafunctions/addcore.tdf" "addcore" "" { Text "c:/altera/quartus41/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" "a_csnbuffer" "" { Text "c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "c:/altera/quartus41/libraries/megafunctions/look_add.tdf" "look_add" "" { Text "c:/altera/quartus41/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "c:/altera/quartus41/libraries/megafunctions/altshift.tdf" "altshift" "" { Text "c:/altera/quartus41/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "13 " "Info: Ignored 13 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "13 " "Info: Ignored 13 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "cp2 " "Info: Promoted clock signal driven by pin cp2 to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "101 " "Info: Implemented 101 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "83 " "Info: Implemented 83 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "1 " "Info: Implemented 1 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 23 14:05:59 2006 " "Info: Processing ended: Mon Oct 23 14:05:59 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}