📄 sys_init.asm
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;----------------------------------------------------------------------
; Configure GP Timers
;----------------------------------------------------------------------
LDP #232 ; Point at EV register page
; Clear all Event Manager registers before proceeding further.
SPLK #1011100001010101b,CAPCON
;5432109876543210
SPLK #0,T1CON
SPLK #0,T2CON
SPLK #0,T3CON
SPLK #0,DBTCON
SPLK #0,COMCON
SPLK #0,T1CNT
SPLK #0,T2CNT
SPLK #0,T3CNT
; Configure GP Timer 1, the PWM time base
SPLK #T1_period_,T1PER ; Init GP Timer 1 period
; Configure GP Timer 2, the sampling and control time base
SPLK #T1_period_,T2PER ; Init GP Timer 2 period
; Configure GP Timer 3
SPLK #T1_period_,T3PER ; Init GP Timer 3 period
;Kill all F. Comp/PWM outputs.
; SPLK #T1_period_,CMPR1
; SPLK #T1_period_,CMPR2
; SPLK #T1_period_,CMPR3
SPLK #0100h,CMPR1
SPLK #0100h,CMPR2
SPLK #0100h,CMPR3
; SPLK #02e4h,SCMPR1
; SPLK #03A4h,SCMPR2
; SPLK #02dah,SCMPR3
*****************************************AD control
; SPLK #0ab4h,SCMPR1
SPLK #04d8h,SCMPR1
; SPLK #0b74h,SCMPR2
SPLK #0598h,SCMPR2
; SPLK #0aaah,SCMPR3
SPLK #04ceh,SCMPR3
; SPLK #10e0h,DBTCON ;Define dead band (16*50=0.8us)
; 5432109876543210
; SPLK #20e0h,DBTCON ;Define dead band (32*50=1.6us)
; SPLK #40e0h,DBTCON ;Define dead band (64*50=3.2us)
; SPLK #28e0h,DBTCON ;Define dead band (40*50=2.0us)
;Let GP Timer compare outputs toggle (to have more things I can
;look at with an oscilloscope).
; SPLK #02dah,T1CMP ;>=0X01F4 is high level, 0x0000 is low
; SPLK #01e4h,T2CMP
; SPLK #01e4h,T3CMP
; SPLK #0aaah,T1CMP ;>=0X01F4 is high level, 0x0000 is low
SPLK #04ceh,T1CMP
; SPLK #09b4h,T2CMP
SPLK #03d8h,T2CMP
; SPLK #09b4h,T3CMP
SPLK #03d8h,T3CMP
**********************************************
; SPLK #0000011001100110b,ACTR ;Full Action Cntl
; 5432109876543210
* bits 15 0: Dir = CCW (n/c)
* bits 14-12 000: D2D1D0 = 000 (n/c)
* bits 11-10 10: PWM6/CMP6 active high
* bits 9-8 01: PWM5/CMP5 active low
* bits 7-6 10: PWM4/CMP4 active high
* bits 5-4 01: PWM3/CMP3 active low
* bits 3-2 01: PWM2/CMP2 active high
* bits 1-0 01: PWM1/CMP1 active low
; SPLK #0000111111111111b,ACTR
SPLK #0000100110011001b,ACTR
SPLK #0000000000101010b,SACTR ;Full Action Cntl
; 5432109876543210
* bits 15-6 Reserved
* bits 5-4 10: PWM9/CMP9 active high
* bits 3-2 10: PWM8/CMP8 active high
* bits 1-0 10: PWM7/CMP7 active high
; Write COMCON twice to enable PWM outputs
SPLK #0000001100000111b,COMCON; Compare Cntl
SPLK #1000001100000111b,COMCON; Compare Cntl
; 5432109876543210
* bit 15 1: Enable Compare/PWM operation
* bits 14-13 00: Load F. Comp. Reg on UF of GPT1
* bit 12 0: Disable Space Vector PWM Mode
* bits 11-10 00: Load ACTR on underflow of GPt1
* bit 9 1: Enable F Compare outputs
* bit 8 1: Enable S Compare outputs
* bit 7 0: Select GP Timer 1 as time base for S Comp Units
* bits 6-5 00: Load SCMPR on Underflow of selected GP Timer
* bits 4-3 00: Load SACTR on underflow of selected GP Timer
* bit 2 1: F. Comp. Unit 3 in PWM mode
* PWM5/CMP5 & PWM6/CMP6 are PWM outputs
* bit 1 1: F. Comp. Unit 2 in PWM mode
* PWM3/CMP3 & PWM4/CMP4 are PWM outputs
* bit 0 1: F. Comp. Unit 1 in PWM mode
* PWM1/CMP1 & PWM2/CMP2 are PWM outputs
; Define GP Timer compare output polarities and actions
SPLK #0000000001010101b,GPTCON
; 5432109876543210
* bits 12-11 00: No GP Timer 3 event starts ADC
* bits 10-9 00: No GP Timer 2 event starts ADC
* bits 8-7 00: No GP Timer 1 event starts ADC
* bit 6 1: Enable GP Timer Compare outputs
* bits 5-4 01: GP Timer 3 comp output active low
* bits 3-2 01: GP Timer 2 comp output active low
* bits 1-0 01: GP Timer 1 comp output active low
SPLK #1001000000000010b,T1CON; Set GP Timer control register
; 5432109876543210
* bit 15 1: FREE = 1
* bit 14 0: SOFT = 0
* bits 13-11 010: continuous-up/down count mode
* bits 10-8 000: Prescaler = /1
* bit 7 0: Reserved
* bit 6 0: disable Timer (counting operation)
* bits 5-4 00: Select internal CLK
* bits 3-2 00: Load GP Timer comp register on underflow
* bit 1 1: GP Timer compare enabled
* bit 0 0: reserved
SPLK #1001011110000010b,T2CON; Set GP Timer 2 control
; 5432109876543210
* bit 15 1: FREE = 1
* bit 14 0: SOFT = 0
* bits 13-11 101: continuous-up count mode
* bits 10-8 000: Prescaler = /1
* bit 7 1: Use Timer ENABLE of GP Timer 1
* bit 6 0: disable timer (counting operation)
* bits 5-4 00: Select internal CLK
* bits 3-2 00: Load GP Timer comp register on underflow
* bit 1 1: GP Timer compare enabled
* bit 0 0: not Use GP Timer 1 PR
; synch w GPT1
SPLK #1001011110000010b,T3CON ; GPT3 in c-up mode
; 5432109876543210
* bit 15 1: FREE = 1
* bit 14 0: SOFT = 0
* bits 13-11 101: continuous-up count mode
* bits 10-8 000: Prescaler = /1
* bit 7 1: Use Timer ENABLE of GP Timer 1
* bit 6 0: disable timer (counting operation)
* bits 5-4 00: Select internal CLK
* bits 3-2 00: Load GP Timer comp register on underflow
* bit 1 1: GP Timer compare enabled
* bit 0 0: not Use Timer 1 PR
; p/s=32 in synch w T1
; ---------------------------------------------------------------------
; Initialize stack pointer
; ---------------------------------------------------------------------
; LAR AR7,#stack_ptr
; ---------------------------------------------------------------------
; Initialize variables
;----------------------------------------------------------------------
; ------------------------------------------------------------------
; Mask/unmask interrupts
; ------------------------------------------------------------------
LDP #232 ; point at EV reg page
SPLK #0ffffh,IFRA ; Clear all Group A int flags
SPLK #0ffffh,IFRB ; Clear all Group B int flags
SPLK #0ffffh,IFRC ; Clear all Group C int flags
SPLK #0200h,IMRA ; Unmask PDPINT,GPT1 UF ints
SPLK #0h,IMRB ; Mask all EV Grp B ints
SPLK #0h,IMRC ; Mask all EV Grp C ints
LDP #0 ; Point at MMR page
SPLK #0000010b,IMR ; Enable int to CPU (no emu int)
SPLK #0ffffh,IFR ; Clear pending int to CPU
SETC OVM;Set overflow protect mode
SETC SXM ;Set sign extension (allow) mode
; -----------------------------------------------------------------
; Enable global interrupt to start real-time operation
; -----------------------------------------------------------------
LDP #232
; Enable global interrupt
SPLK #1001000001000010b,T1CON; Set GP Timer control register
; 5432109876543210
* bit 15 1: FREE = 1
* bit 14 0: SOFT = 0
* bits 13-11 010: continuous-up/down count mode
* bits 10-8 000: Prescaler = /1
* bit 7 0: Reserved
* bit 6 1: Enable Timer (counting operation)
* bits 5-4 00: Select internal CLK
* bits 3-2 00: Load GP Timer comp register on underflow
* bit 1 1: GP Timer compare enabled
* bit 0 0: reserved
SPLK #1001011111000010b,T2CON; Set GP Timer 2 control
; 5432109876543210
* bit 15 1: FREE = 1
* bit 14 0: SOFT = 0
* bits 13-11 101: continuous-up count mode
* bits 10-8 000: Prescaler = /1
* bit 7 1: Use Timer ENABLE of GP Timer 1
* bit 6 1: Enable timer (counting operation)
* bits 5-4 00: Select internal CLK
* bits 3-2 00: Load GP Timer comp register on underflow
* bit 1 1: GP Timer compare enabled
* bit 0 0: not Use GP Timer 1 PR
; synch w GPT1
SPLK #1001011111000010b,T3CON ; GPT3 in c-up mode
; 5432109876543210
* bit 15 1: FREE = 1
* bit 14 0: SOFT = 0
* bits 13-11 101: continuous-up count mode
* bits 10-8 000: Prescaler = /1
* bit 7 1: Use Timer ENABLE of GP Timer 1
* bit 6 1: Enable timer (counting operation)
* bits 5-4 00: Select internal CLK
* bits 3-2 00: Load GP Timer comp register on underflow
* bit 1 1: GP Timer compare enabled
* bit 0 0: not Use Timer 1 PR
; p/s=32 in synch w T1
EINT
RET
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