spi_master_interface_bt_top.srr

a verilog prigram for SPI

$ Start of Compile
#Tue Mar 18 21:53:47 2008

Synplicity Verilog Compiler, version Compilers 2.6.0, Build 102R, built Jan 27 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved

@I::"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\clk_gen.v"
@I::"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\counter_4bit.v"
@I::"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\counter_5bit.v"
@I::"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\mcu_interface.v"
@I::"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\rec_shift.v"
@I::"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_controller.v"
@I::"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_interface.v"
@I::"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_master.v"
@I::"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_master_interface.v"
@I::"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_master_interface_bt.v"
@I::"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\state_controller.v"
@I::"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\tx_shift.v"
@I::"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\state_controller_top.v"
@I::"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_master_interface_bt_top.v"
Verilog syntax check successful!
File D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_master_interface_bt.v changed - recompiling
Selecting top level module spi_master_interface_bt_top
Synthesizing module mcu_interface
@N: CL201 :"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\mcu_interface.v":125:3:125:8|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Synthesizing module state_controller
@N: CL201 :"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\state_controller.v":166:3:166:8|Trying to extract state machine for register address
Extracted state machine for register address
State machine has 4 reachable states with original encodings of:
   001
   010
   011
   100
@N: CL201 :"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\state_controller.v":81:3:81:8|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 13 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
   1100
Synthesizing module state_controller_top
Synthesizing module counter_5bit
Synthesizing module clk_gen
Synthesizing module tx_shift
Synthesizing module rec_shift
@W: CL170 :"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\rec_shift.v":41:3:41:8|Pruning bit <7> of data_int[7:0] - not in use ...

Synthesizing module counter_4bit
Synthesizing module spi_controller
@W: CL118 :"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_controller.v":116:9:116:12|Latch generated from always block for signal next_state[3:0], probably caused by a missing assignment in an if or case stmt
Synthesizing module spi_interface
Synthesizing module spi_master
Synthesizing module spi_master_interface
@N: CL201 :"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_master_interface.v":32:3:32:8|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 8 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
   111
Synthesizing module spi_master_interface_bt
@W: CL169 :"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_master_interface_bt.v":116:3:116:8|Pruning Register ram_3_[7:0] 

@W: CL169 :"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_master_interface_bt.v":116:3:116:8|Pruning Register ram_0_[7:0] 

@W: CL169 :"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_master_interface_bt.v":116:3:116:8|Pruning Register ram_1_[7:0] 

@W: CL169 :"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_master_interface_bt.v":116:3:116:8|Pruning Register ram_2_[7:0] 

@N: CL201 :"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_master_interface_bt.v":29:3:29:8|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 9 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
@W: CL159 :"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_master_interface_bt.v":10:14:10:26|Input data_byte_int is unused
@W: CL159 :"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_master_interface_bt.v":12:9:12:15|Input load_rr is unused
@W: CL159 :"D:\XILINX\SPI_T\SPI_COOLRUNNER_VER3\spi_master_interface_bt.v":14:14:14:21|Input rec_data is unused
Synthesizing module spi_master_interface_bt_top
@END
Process took 0h:0m:1s realtime, 0h:0m:1s cputime