spi_master_interface_bt_top.plg

a verilog prigram for SPI

@P:  Worst Slack : -0.826
@P:  spi_master_interface_bt_top|clk - Estimated Frequency : 127.9 MHz
@P:  spi_master_interface_bt_top|clk - Requested Frequency : 162.2 MHz
@P:  spi_master_interface_bt_top|clk - Estimated Period : 7.816
@P:  spi_master_interface_bt_top|clk - Requested Period : 6.164
@P:  spi_master_interface_bt_top|clk - Slack : -0.826
@P:  spi_master_interface_bt_top|sck_inferred_clock - Estimated Frequency : 228.0 MHz
@P:  spi_master_interface_bt_top|sck_inferred_clock - Requested Frequency : 268.0 MHz
@P:  spi_master_interface_bt_top|sck_inferred_clock - Estimated Period : 4.386
@P:  spi_master_interface_bt_top|sck_inferred_clock - Requested Period : 3.731
@P:  spi_master_interface_bt_top|sck_inferred_clock - Slack : -0.655
@P:  System - Estimated Frequency : 338.6 MHz
@P:  System - Requested Frequency : 430.3 MHz
@P:  System - Estimated Period : 2.954
@P:  System - Requested Period : 2.324
@P:  System - Slack : -0.630
@P: spi_master_interface_bt_top Part : xc2v40cs144-6
@P: spi_master_interface_bt_top I/O primitives : 22
@P: spi_master_interface_bt_top I/O Register bits : 1
@P: spi_master_interface_bt_top Register bits (Non I/O) : 199 (38%)
@P: spi_master_interface_bt_top Total Luts : 340 (66%)