counter_4bit.v

来自「a verilog prigram for SPI」· Verilog 代码 · 共 19 行

module counter_4bit(clk,clr,cnt_en,q);
    
   input clk,clr,cnt_en;
   output [3:0]q;
   reg [3:0]q_in;
   
   assign q=q_in;
   
   always @(posedge clk or negedge clr)
      begin
         if (clr==0)
            q_in<=4'b0000;
         else if (cnt_en==1)
                 q_in<=q_in+1;
              //else q_in<=q_in;
      end
      
endmodule