spi_t.prj

a verilog prigram for SPI

#-- Synplicity, Inc.
#-- Version 7.5.1     
#-- Project file D:\Xilinx\spi_t\spi_coolrunner_ver3\spi_t.prj
#-- Written on Tue Mar 18 22:34:02 2008


#add_file options
add_file -verilog "clk_gen.v"
add_file -verilog "counter_4bit.v"
add_file -verilog "counter_5bit.v"
add_file -verilog "mcu_interface.v"
add_file -verilog "rec_shift.v"
add_file -verilog "spi_controller.v"
add_file -verilog "spi_interface.v"
add_file -verilog "spi_master.v"
add_file -verilog "spi_master_interface.v"
add_file -verilog "spi_master_interface_bt.v"
add_file -verilog "spi_master_interface_bt_top.v"
add_file -verilog "spi_master_interface_bt_top_tb.v"
add_file -verilog "state_controller.v"
add_file -verilog "state_controller_top.v"
add_file -verilog "tx_shift.v"


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology VIRTEX2
set_option -part XC2V40
set_option -package CS144
set_option -speed_grade -6

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -use_fsm_explorer 0

#map options
set_option -frequency auto
set_option -fanout_limit 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -fixgatedclocks 0
set_option -modular 0
set_option -retiming 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/tx_shift.edf"

#implementation attributes
set_option -vlog_std v2001
set_option -auto_constrain_io 0
impl -active "rev_1"