top_tb.v

来自「不错的Quartus II 与modelsim结合仿真简介笔记」· Verilog 代码 · 共 71 行

`timescale 1 ps/ 1 ps
module top_tb();
                            
reg	  aclr;
reg	  clock;
reg	[7:0]  data;
reg	  enable;
reg	  load;
reg	  shiftin;
                                        
wire [7:0] q;

lpm_shift tb (
	.aclr ( aclr ),
	.clock (clock),
	.data (data),
	.enable ( enable ),
	.load (load),
	.shiftin ( shiftin ),
	.q ( q )
);

//aclr
initial
begin
    aclr = 1'b1;
    aclr = # 5000 1'b0;
end

// clock
always
begin
	clock = 1'b0;
	clock = #50000 1'b1;
	clock = #50000 1'b0;
end 

// enable
initial
begin
	enable = 1'b1;
end 

// data
initial
begin
	data = 8'b10101011;
end 

//load
initial
begin
	load = 1'b0;
	# 150000 load = 1'b1;
	load = # 200000 1'b0;
end


// shiftin
initial
begin
	shiftin = 1'b0;
	#1555000 shiftin =  1'b1;
	#2365000 shiftin =  1'b0;
	#5070000 shiftin =  1'b1;
	#7120000 shiftin =  1'b1;
	shiftin = #9144000 1'b0;
end 


endmodule