watch.fit.qmsg

基于CYCLONG II的自己编的电子时钟.早期作品了,可能这方面的资料也比较多,但是个人思路不同,希望我的程序能给朋友们提供些须帮助.

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.141 ns register register " "Info: Estimated most critical path is register to register delay of 2.141 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour:dff4\|cout\[0\] 1 REG LAB_X1_Y2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X1_Y2; Fanout = 4; REG Node = 'hour:dff4\|cout\[0\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { hour:dff4|cout[0] } "NODE_NAME" } } { "hour.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/hour.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.455 ns) + CELL(0.414 ns) 0.869 ns hour:dff4\|Add0~61 2 COMB LAB_X1_Y2 2 " "Info: 2: + IC(0.455 ns) + CELL(0.414 ns) = 0.869 ns; Loc. = LAB_X1_Y2; Fanout = 2; COMB Node = 'hour:dff4\|Add0~61'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.869 ns" { hour:dff4|cout[0] hour:dff4|Add0~61 } "NODE_NAME" } } { "e:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.940 ns hour:dff4\|Add0~63 3 COMB LAB_X1_Y2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.940 ns; Loc. = LAB_X1_Y2; Fanout = 2; COMB Node = 'hour:dff4\|Add0~63'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { hour:dff4|Add0~61 hour:dff4|Add0~63 } "NODE_NAME" } } { "e:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.011 ns hour:dff4\|Add0~65 4 COMB LAB_X1_Y2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.011 ns; Loc. = LAB_X1_Y2; Fanout = 2; COMB Node = 'hour:dff4\|Add0~65'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { hour:dff4|Add0~63 hour:dff4|Add0~65 } "NODE_NAME" } } { "e:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.082 ns hour:dff4\|Add0~67 5 COMB LAB_X1_Y2 1 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.082 ns; Loc. = LAB_X1_Y2; Fanout = 1; COMB Node = 'hour:dff4\|Add0~67'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { hour:dff4|Add0~65 hour:dff4|Add0~67 } "NODE_NAME" } } { "e:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.492 ns hour:dff4\|Add0~68 6 COMB LAB_X1_Y2 1 " "Info: 6: + IC(0.000 ns) + CELL(0.410 ns) = 1.492 ns; Loc. = LAB_X1_Y2; Fanout = 1; COMB Node = 'hour:dff4\|Add0~68'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { hour:dff4|Add0~67 hour:dff4|Add0~68 } "NODE_NAME" } } { "e:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "e:/altera/61/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.438 ns) 2.057 ns hour:dff4\|cout~84 7 COMB LAB_X1_Y2 1 " "Info: 7: + IC(0.127 ns) + CELL(0.438 ns) = 2.057 ns; Loc. = LAB_X1_Y2; Fanout = 1; COMB Node = 'hour:dff4\|cout~84'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { hour:dff4|Add0~68 hour:dff4|cout~84 } "NODE_NAME" } } { "hour.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/hour.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.141 ns hour:dff4\|cout\[4\] 8 REG LAB_X1_Y2 4 " "Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 2.141 ns; Loc. = LAB_X1_Y2; Fanout = 4; REG Node = 'hour:dff4\|cout\[4\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { hour:dff4|cout~84 hour:dff4|cout[4] } "NODE_NAME" } } { "hour.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/hour.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.559 ns ( 72.82 % ) " "Info: Total cell delay = 1.559 ns ( 72.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.582 ns ( 27.18 % ) " "Info: Total interconnect delay = 0.582 ns ( 27.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.141 ns" { hour:dff4|cout[0] hour:dff4|Add0~61 hour:dff4|Add0~63 hour:dff4|Add0~65 hour:dff4|Add0~67 hour:dff4|Add0~68 hour:dff4|cout~84 hour:dff4|cout[4] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X14_Y0 X28_Y14 " "Info: The peak interconnect region extends from location X14_Y0 to location X28_Y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "19 " "Warning: Found 19 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "s1\[0\] 0 " "Info: Pin \"s1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "s1\[1\] 0 " "Info: Pin \"s1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "s1\[2\] 0 " "Info: Pin \"s1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "s1\[3\] 0 " "Info: Pin \"s1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "m1\[0\] 0 " "Info: Pin \"m1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "m1\[1\] 0 " "Info: Pin \"m1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "m1\[2\] 0 " "Info: Pin \"m1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "m1\[3\] 0 " "Info: Pin \"m1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "s2\[0\] 0 " "Info: Pin \"s2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "s2\[1\] 0 " "Info: Pin \"s2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "s2\[2\] 0 " "Info: Pin \"s2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "m2\[0\] 0 " "Info: Pin \"m2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "m2\[1\] 0 " "Info: Pin \"m2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "m2\[2\] 0 " "Info: Pin \"m2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "h\[0\] 0 " "Info: Pin \"h\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "h\[1\] 0 " "Info: Pin \"h\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "h\[2\] 0 " "Info: Pin \"h\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "h\[3\] 0 " "Info: Pin \"h\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "h\[4\] 0 " "Info: Pin \"h\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "167 " "Info: Allocated 167 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 17 11:10:33 2007 " "Info: Processing ended: Thu May 17 11:10:33 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}