watch.tan.qmsg

基于CYCLONG II的自己编的电子时钟.早期作品了,可能这方面的资料也比较多,但是个人思路不同,希望我的程序能给朋友们提供些须帮助.

{ "Info" "ITDB_FULL_TCO_RESULT" "clk h\[0\] hour:dff4\|cout\[0\] 10.110 ns register " "Info: tco from clock \"clk\" to destination pin \"h\[0\]\" through register \"hour:dff4\|cout\[0\]\" is 10.110 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.549 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.549 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "watch_a.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/watch_a.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "watch_a.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/watch_a.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.787 ns) 2.590 ns second:dff2\|cout2\[2\] 3 REG LCFF_X27_Y7_N7 4 " "Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.590 ns; Loc. = LCFF_X27_Y7_N7; Fanout = 4; REG Node = 'second:dff2\|cout2\[2\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.489 ns" { clk~clkctrl second:dff2|cout2[2] } "NODE_NAME" } } { "second.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/second.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.597 ns) + CELL(0.000 ns) 3.187 ns second:dff2\|cout2\[2\]~clkctrl 4 COMB CLKCTRL_G6 7 " "Info: 4: + IC(0.597 ns) + CELL(0.000 ns) = 3.187 ns; Loc. = CLKCTRL_G6; Fanout = 7; COMB Node = 'second:dff2\|cout2\[2\]~clkctrl'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.597 ns" { second:dff2|cout2[2] second:dff2|cout2[2]~clkctrl } "NODE_NAME" } } { "second.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/second.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.689 ns) + CELL(0.787 ns) 4.663 ns minute:dff3\|cout2\[2\] 5 REG LCFF_X1_Y6_N1 4 " "Info: 5: + IC(0.689 ns) + CELL(0.787 ns) = 4.663 ns; Loc. = LCFF_X1_Y6_N1; Fanout = 4; REG Node = 'minute:dff3\|cout2\[2\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.476 ns" { second:dff2|cout2[2]~clkctrl minute:dff3|cout2[2] } "NODE_NAME" } } { "minute.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/minute.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.641 ns) + CELL(0.000 ns) 5.304 ns minute:dff3\|cout2\[2\]~clkctrl 6 COMB CLKCTRL_G3 5 " "Info: 6: + IC(0.641 ns) + CELL(0.000 ns) = 5.304 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'minute:dff3\|cout2\[2\]~clkctrl'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.641 ns" { minute:dff3|cout2[2] minute:dff3|cout2[2]~clkctrl } "NODE_NAME" } } { "minute.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/minute.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.708 ns) + CELL(0.537 ns) 6.549 ns hour:dff4\|cout\[0\] 7 REG LCFF_X1_Y2_N15 4 " "Info: 7: + IC(0.708 ns) + CELL(0.537 ns) = 6.549 ns; Loc. = LCFF_X1_Y2_N15; Fanout = 4; REG Node = 'hour:dff4\|cout\[0\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.245 ns" { minute:dff3|cout2[2]~clkctrl hour:dff4|cout[0] } "NODE_NAME" } } { "hour.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/hour.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.090 ns ( 47.18 % ) " "Info: Total cell delay = 3.090 ns ( 47.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.459 ns ( 52.82 % ) " "Info: Total interconnect delay = 3.459 ns ( 52.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.549 ns" { clk clk~clkctrl second:dff2|cout2[2] second:dff2|cout2[2]~clkctrl minute:dff3|cout2[2] minute:dff3|cout2[2]~clkctrl hour:dff4|cout[0] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.549 ns" { clk clk~combout clk~clkctrl second:dff2|cout2[2] second:dff2|cout2[2]~clkctrl minute:dff3|cout2[2] minute:dff3|cout2[2]~clkctrl hour:dff4|cout[0] } { 0.000ns 0.000ns 0.122ns 0.702ns 0.597ns 0.689ns 0.641ns 0.708ns } { 0.000ns 0.979ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "hour.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/hour.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.311 ns + Longest register pin " "Info: + Longest register to pin delay is 3.311 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour:dff4\|cout\[0\] 1 REG LCFF_X1_Y2_N15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y2_N15; Fanout = 4; REG Node = 'hour:dff4\|cout\[0\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { hour:dff4|cout[0] } "NODE_NAME" } } { "hour.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/hour.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(2.769 ns) 3.311 ns h\[0\] 2 PIN PIN_L4 0 " "Info: 2: + IC(0.542 ns) + CELL(2.769 ns) = 3.311 ns; Loc. = PIN_L4; Fanout = 0; PIN Node = 'h\[0\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.311 ns" { hour:dff4|cout[0] h[0] } "NODE_NAME" } } { "watch_a.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/watch_a.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.769 ns ( 83.63 % ) " "Info: Total cell delay = 2.769 ns ( 83.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.542 ns ( 16.37 % ) " "Info: Total interconnect delay = 0.542 ns ( 16.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.311 ns" { hour:dff4|cout[0] h[0] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.311 ns" { hour:dff4|cout[0] h[0] } { 0.000ns 0.542ns } { 0.000ns 2.769ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.549 ns" { clk clk~clkctrl second:dff2|cout2[2] second:dff2|cout2[2]~clkctrl minute:dff3|cout2[2] minute:dff3|cout2[2]~clkctrl hour:dff4|cout[0] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "6.549 ns" { clk clk~combout clk~clkctrl second:dff2|cout2[2] second:dff2|cout2[2]~clkctrl minute:dff3|cout2[2] minute:dff3|cout2[2]~clkctrl hour:dff4|cout[0] } { 0.000ns 0.000ns 0.122ns 0.702ns 0.597ns 0.689ns 0.641ns 0.708ns } { 0.000ns 0.979ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.311 ns" { hour:dff4|cout[0] h[0] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "3.311 ns" { hour:dff4|cout[0] h[0] } { 0.000ns 0.542ns } { 0.000ns 2.769ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "100 " "Info: Allocated 100 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 17 11:10:43 2007 " "Info: Processing ended: Thu May 17 11:10:43 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}