watch.map.qmsg

基于CYCLONG II的自己编的电子时钟.早期作品了,可能这方面的资料也比较多,但是个人思路不同,希望我的程序能给朋友们提供些须帮助.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Web Edition " "Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 17 11:10:23 2007 " "Info: Processing started: Thu May 17 11:10:23 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off watch -c watch " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off watch -c watch" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "second.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file second.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 second-behave " "Info: Found design unit 1: second-behave" {  } { { "second.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/second.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 second " "Info: Found entity 1: second" {  } { { "second.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/second.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "minute.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file minute.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 minute-behave " "Info: Found design unit 1: minute-behave" {  } { { "minute.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/minute.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 minute " "Info: Found entity 1: minute" {  } { { "minute.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/minute.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "hour.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file hour.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 hour-behave " "Info: Found design unit 1: hour-behave" {  } { { "hour.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/hour.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 hour " "Info: Found entity 1: hour" {  } { { "hour.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/hour.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock-behave " "Info: Found design unit 1: clock-behave" {  } { { "clock.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/clock.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/clock.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "watch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file watch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 watch-behave " "Info: Found design unit 1: watch-behave" {  } { { "watch.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/watch.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 watch " "Info: Found entity 1: watch" {  } { { "watch.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/watch.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "watch_a.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file watch_a.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 watch_a-behave " "Info: Found design unit 1: watch_a-behave" {  } { { "watch_a.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/watch_a.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 watch_a " "Info: Found entity 1: watch_a" {  } { { "watch_a.vhd" "" { Text "D:/works/模电/lab/VHDL/watch/watch_a.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "watch_a " "Info: Elaborating entity \"watch_a\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "second second:dff2 " "Info: Elaborating entity \"second\" for hierarchy \"second:dff2\"" {  } { { "watch_a.vhd" "dff2" { Text "D:/works/模电/lab/VHDL/watch/watch_a.vhd" 45 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "minute minute:dff3 " "Info: Elaborating entity \"minute\" for hierarchy \"minute:dff3\"" {  } { { "watch_a.vhd" "dff3" { Text "D:/works/模电/lab/VHDL/watch/watch_a.vhd" 46 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hour hour:dff4 " "Info: Elaborating entity \"hour\" for hierarchy \"hour:dff4\"" {  } { { "watch_a.vhd" "dff4" { Text "D:/works/模电/lab/VHDL/watch/watch_a.vhd" 47 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "45 " "Info: Implemented 45 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "19 " "Info: Implemented 19 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "24 " "Info: Implemented 24 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "141 " "Info: Allocated 141 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 17 11:10:26 2007 " "Info: Processing ended: Thu May 17 11:10:26 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}