second.vhd

来自「基于CYCLONG II的自己编的电子时钟.早期作品了,可能这方面的资料也比较多」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY second IS
  PORT(clk,clear:IN STD_LOGIC;
       cout1:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
       cout2:BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0));
END second;
ARCHITECTURE behave OF second IS
  BEGIN
    PROCESS(clk,clear)
  BEGIN
   if(clear='1')then
   cout1<="0000";
   cout2<="000";
   elsif(clk'EVENT AND clk='0')THEN
       if(cout1=9)then
       cout1<="0000";
       if(cout2=5)then
       cout2<="000";
       else cout2<=cout2+1;
       end if;
       else cout1<=cout1+1;
       END IF;
   END IF;
  END PROCESS;
END behave;