dds.map.qmsg

基于CYCLONE II的程序,DDS原理的函数信号发生器.采用查表法实现.各位可以参考.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Web Edition " "Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 23 19:46:49 2007 " "Info: Processing started: Wed May 23 19:46:49 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DDS -c dds " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDS -c dds" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 test " "Info: Found entity 1: test" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "test " "Info: Elaborating entity \"test\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "add_sub.vhd 2 1 " "Warning: Using design file add_sub.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add_sub-SYN " "Info: Found design unit 1: add_sub-SYN" {  } { { "add_sub.vhd" "" { Text "D:/works/模电/lab/VHDL/dds/add_sub.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 add_sub " "Info: Found entity 1: add_sub" {  } { { "add_sub.vhd" "" { Text "D:/works/模电/lab/VHDL/dds/add_sub.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub add_sub:inst " "Info: Elaborating entity \"add_sub\" for hierarchy \"add_sub:inst\"" {  } { { "test.bdf" "inst" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 200 296 456 296 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/61/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/61/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/altera/61/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub add_sub:inst\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"add_sub:inst\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "add_sub.vhd" "lpm_add_sub_component" { Text "D:/works/模电/lab/VHDL/dds/add_sub.vhd" 78 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "add_sub:inst\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"add_sub:inst\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "add_sub.vhd" "" { Text "D:/works/模电/lab/VHDL/dds/add_sub.vhd" 78 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_blg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_blg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_blg " "Info: Found entity 1: add_sub_blg" {  } { { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_blg add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated " "Info: Elaborating entity \"add_sub_blg\" for hierarchy \"add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "e:/altera/61/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "25 " "Info: Implemented 25 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 23 19:46:51 2007 " "Info: Processing ended: Wed May 23 19:46:51 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}