dds.tan.qmsg

来自「基于CYCLONE II的程序,DDS原理的函数信号发生器.采用查表法实现.各位」· QMSG 代码 · 共 10 行 · 第 1/4 页

{ "Info" "ITDB_FULL_TCO_RESULT" "clk pin_out\[6\] add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[6\] 6.969 ns register " "Info: tco from clock \"clk\" to destination pin \"pin_out\[6\]\" through register \"add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[6\]\" is 6.969 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.358 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.358 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 248 104 272 264 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 248 104 272 264 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.710 ns) + CELL(0.537 ns) 2.358 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[6\] 3 REG LCFF_X20_Y4_N15 3 " "Info: 3: + IC(0.710 ns) + CELL(0.537 ns) = 2.358 ns; Loc. = LCFF_X20_Y4_N15; Fanout = 3; REG Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[6\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.247 ns" { clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.72 % ) " "Info: Total cell delay = 1.526 ns ( 64.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.832 ns ( 35.28 % ) " "Info: Total interconnect delay = 0.832 ns ( 35.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.358 ns" { clk clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.358 ns" { clk clk~combout clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] } { 0.000ns 0.000ns 0.122ns 0.710ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.361 ns + Longest register pin " "Info: + Longest register to pin delay is 4.361 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[6\] 1 REG LCFF_X20_Y4_N15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y4_N15; Fanout = 3; REG Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[6\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.573 ns) + CELL(2.788 ns) 4.361 ns pin_out\[6\] 2 PIN PIN_126 0 " "Info: 2: + IC(1.573 ns) + CELL(2.788 ns) = 4.361 ns; Loc. = PIN_126; Fanout = 0; PIN Node = 'pin_out\[6\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.361 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] pin_out[6] } "NODE_NAME" } } { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 320 528 704 336 "pin_out\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.788 ns ( 63.93 % ) " "Info: Total cell delay = 2.788 ns ( 63.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.573 ns ( 36.07 % ) " "Info: Total interconnect delay = 1.573 ns ( 36.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.361 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] pin_out[6] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.361 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] pin_out[6] } { 0.000ns 1.573ns } { 0.000ns 2.788ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.358 ns" { clk clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.358 ns" { clk clk~combout clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] } { 0.000ns 0.000ns 0.122ns 0.710ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.361 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] pin_out[6] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "4.361 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] pin_out[6] } { 0.000ns 1.573ns } { 0.000ns 2.788ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\] pin_in\[0\] clk 0.066 ns register " "Info: th for register \"add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\]\" (data pin = \"pin_in\[0\]\", clock pin = \"clk\") is 0.066 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.358 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.358 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 248 104 272 264 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 248 104 272 264 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.710 ns) + CELL(0.537 ns) 2.358 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\] 3 REG LCFF_X20_Y4_N3 3 " "Info: 3: + IC(0.710 ns) + CELL(0.537 ns) = 2.358 ns; Loc. = LCFF_X20_Y4_N3; Fanout = 3; REG Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.247 ns" { clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.72 % ) " "Info: Total cell delay = 1.526 ns ( 64.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.832 ns ( 35.28 % ) " "Info: Total interconnect delay = 0.832 ns ( 35.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.358 ns" { clk clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.358 ns" { clk clk~combout clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } { 0.000ns 0.000ns 0.122ns 0.710ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.558 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.558 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns pin_in\[0\] 1 PIN PIN_88 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_88; Fanout = 2; PIN Node = 'pin_in\[0\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[0] } "NODE_NAME" } } { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 352 120 288 368 "pin_in\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.437 ns) 2.474 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\]~39 2 COMB LCCOMB_X20_Y4_N2 1 " "Info: 2: + IC(1.038 ns) + CELL(0.437 ns) = 2.474 ns; Loc. = LCCOMB_X20_Y4_N2; Fanout = 1; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\]~39'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.475 ns" { pin_in[0] add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]~39 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.558 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\] 3 REG LCFF_X20_Y4_N3 3 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.558 ns; Loc. = LCFF_X20_Y4_N3; Fanout = 3; REG Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]~39 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.520 ns ( 59.42 % ) " "Info: Total cell delay = 1.520 ns ( 59.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.038 ns ( 40.58 % ) " "Info: Total interconnect delay = 1.038 ns ( 40.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.558 ns" { pin_in[0] add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]~39 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.558 ns" { pin_in[0] pin_in[0]~combout add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]~39 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } { 0.000ns 0.000ns 1.038ns 0.000ns } { 0.000ns 0.999ns 0.437ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.358 ns" { clk clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.358 ns" { clk clk~combout clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } { 0.000ns 0.000ns 0.122ns 0.710ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.558 ns" { pin_in[0] add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]~39 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.558 ns" { pin_in[0] pin_in[0]~combout add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]~39 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } { 0.000ns 0.000ns 1.038ns 0.000ns } { 0.000ns 0.999ns 0.437ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "100 " "Info: Allocated 100 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed May 23 19:47:05 2007 " "Info: Processing ended: Wed May 23 19:47:05 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}