📄 dds.tan.qmsg

📁 基于CYCLONE II的程序,DDS原理的函数信号发生器.采用查表法实现.各位可以参考.
💻 QMSG
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 248 104 272 264 "clk" "" } } } } { "e:/altera/61/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/61/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\] add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\] 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\]\" and destination register \"add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.708 ns + Longest register register " "Info: + Longest register to register delay is 1.708 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\] 1 REG LCFF_X20_Y4_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y4_N3; Fanout = 3; REG Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.307 ns) + CELL(0.393 ns) 0.700 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\]~40 2 COMB LCCOMB_X20_Y4_N2 2 " "Info: 2: + IC(0.307 ns) + CELL(0.393 ns) = 0.700 ns; Loc. = LCCOMB_X20_Y4_N2; Fanout = 2; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\]~40'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.700 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]~40 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.771 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[1\]~41 3 COMB LCCOMB_X20_Y4_N4 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.771 ns; Loc. = LCCOMB_X20_Y4_N4; Fanout = 2; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[1\]~41'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]~40 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1]~41 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.842 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[2\]~42 4 COMB LCCOMB_X20_Y4_N6 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.842 ns; Loc. = LCCOMB_X20_Y4_N6; Fanout = 2; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[2\]~42'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1]~41 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2]~42 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.913 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[3\]~43 5 COMB LCCOMB_X20_Y4_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 0.913 ns; Loc. = LCCOMB_X20_Y4_N8; Fanout = 2; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[3\]~43'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2]~42 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3]~43 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.984 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[4\]~44 6 COMB LCCOMB_X20_Y4_N10 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 0.984 ns; Loc. = LCCOMB_X20_Y4_N10; Fanout = 2; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[4\]~44'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3]~43 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4]~44 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.055 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[5\]~45 7 COMB LCCOMB_X20_Y4_N12 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.055 ns; Loc. = LCCOMB_X20_Y4_N12; Fanout = 2; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[5\]~45'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4]~44 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5]~45 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 1.214 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[6\]~46 8 COMB LCCOMB_X20_Y4_N14 1 " "Info: 8: + IC(0.000 ns) + CELL(0.159 ns) = 1.214 ns; Loc. = LCCOMB_X20_Y4_N14; Fanout = 1; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[6\]~46'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5]~45 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]~46 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.624 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\]~32 9 COMB LCCOMB_X20_Y4_N16 1 " "Info: 9: + IC(0.000 ns) + CELL(0.410 ns) = 1.624 ns; Loc. = LCCOMB_X20_Y4_N16; Fanout = 1; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\]~32'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]~46 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]~32 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.708 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\] 10 REG LCFF_X20_Y4_N17 2 " "Info: 10: + IC(0.000 ns) + CELL(0.084 ns) = 1.708 ns; Loc. = LCFF_X20_Y4_N17; Fanout = 2; REG Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]~32 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.401 ns ( 82.03 % ) " "Info: Total cell delay = 1.401 ns ( 82.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.307 ns ( 17.97 % ) " "Info: Total interconnect delay = 0.307 ns ( 17.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.708 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]~40 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1]~41 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2]~42 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3]~43 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4]~44 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5]~45 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]~46 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]~32 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "1.708 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]~40 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1]~41 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2]~42 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3]~43 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4]~44 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5]~45 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]~46 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]~32 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } { 0.000ns 0.307ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.410ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.358 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.358 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 248 104 272 264 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 248 104 272 264 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.710 ns) + CELL(0.537 ns) 2.358 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\] 3 REG LCFF_X20_Y4_N17 2 " "Info: 3: + IC(0.710 ns) + CELL(0.537 ns) = 2.358 ns; Loc. = LCFF_X20_Y4_N17; Fanout = 2; REG Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.247 ns" { clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.72 % ) " "Info: Total cell delay = 1.526 ns ( 64.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.832 ns ( 35.28 % ) " "Info: Total interconnect delay = 0.832 ns ( 35.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.358 ns" { clk clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.358 ns" { clk clk~combout clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } { 0.000ns 0.000ns 0.122ns 0.710ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.358 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.358 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 248 104 272 264 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 248 104 272 264 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.710 ns) + CELL(0.537 ns) 2.358 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\] 3 REG LCFF_X20_Y4_N3 3 " "Info: 3: + IC(0.710 ns) + CELL(0.537 ns) = 2.358 ns; Loc. = LCFF_X20_Y4_N3; Fanout = 3; REG Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[0\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.247 ns" { clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.72 % ) " "Info: Total cell delay = 1.526 ns ( 64.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.832 ns ( 35.28 % ) " "Info: Total interconnect delay = 0.832 ns ( 35.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.358 ns" { clk clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.358 ns" { clk clk~combout clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } { 0.000ns 0.000ns 0.122ns 0.710ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.358 ns" { clk clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.358 ns" { clk clk~combout clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } { 0.000ns 0.000ns 0.122ns 0.710ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.358 ns" { clk clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.358 ns" { clk clk~combout clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } { 0.000ns 0.000ns 0.122ns 0.710ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.708 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]~40 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1]~41 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2]~42 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3]~43 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4]~44 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5]~45 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]~46 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]~32 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "1.708 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]~40 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1]~41 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2]~42 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3]~43 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4]~44 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5]~45 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]~46 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]~32 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } { 0.000ns 0.307ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.410ns 0.084ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.358 ns" { clk clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.358 ns" { clk clk~combout clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } { 0.000ns 0.000ns 0.122ns 0.710ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.358 ns" { clk clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.358 ns" { clk clk~combout clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] } { 0.000ns 0.000ns 0.122ns 0.710ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } {  } {  } "" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\] pin_in\[1\] clk 5.502 ns register " "Info: tsu for register \"add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\]\" (data pin = \"pin_in\[1\]\", clock pin = \"clk\") is 5.502 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.896 ns + Longest pin register " "Info: + Longest pin to register delay is 7.896 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns pin_in\[1\] 1 PIN PIN_113 2 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_113; Fanout = 2; PIN Node = 'pin_in\[1\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[1] } "NODE_NAME" } } { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 352 120 288 368 "pin_in\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.695 ns) + CELL(0.414 ns) 6.959 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[1\]~41 2 COMB LCCOMB_X20_Y4_N4 2 " "Info: 2: + IC(5.695 ns) + CELL(0.414 ns) = 6.959 ns; Loc. = LCCOMB_X20_Y4_N4; Fanout = 2; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[1\]~41'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "6.109 ns" { pin_in[1] add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1]~41 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.030 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[2\]~42 3 COMB LCCOMB_X20_Y4_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 7.030 ns; Loc. = LCCOMB_X20_Y4_N6; Fanout = 2; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[2\]~42'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1]~41 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2]~42 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.101 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[3\]~43 4 COMB LCCOMB_X20_Y4_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 7.101 ns; Loc. = LCCOMB_X20_Y4_N8; Fanout = 2; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[3\]~43'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2]~42 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3]~43 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.172 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[4\]~44 5 COMB LCCOMB_X20_Y4_N10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 7.172 ns; Loc. = LCCOMB_X20_Y4_N10; Fanout = 2; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[4\]~44'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3]~43 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4]~44 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 7.243 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[5\]~45 6 COMB LCCOMB_X20_Y4_N12 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 7.243 ns; Loc. = LCCOMB_X20_Y4_N12; Fanout = 2; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[5\]~45'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4]~44 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5]~45 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 7.402 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[6\]~46 7 COMB LCCOMB_X20_Y4_N14 1 " "Info: 7: + IC(0.000 ns) + CELL(0.159 ns) = 7.402 ns; Loc. = LCCOMB_X20_Y4_N14; Fanout = 1; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[6\]~46'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5]~45 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]~46 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 7.812 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\]~32 8 COMB LCCOMB_X20_Y4_N16 1 " "Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 7.812 ns; Loc. = LCCOMB_X20_Y4_N16; Fanout = 1; COMB Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\]~32'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]~46 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]~32 } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 7.896 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\] 9 REG LCFF_X20_Y4_N17 2 " "Info: 9: + IC(0.000 ns) + CELL(0.084 ns) = 7.896 ns; Loc. = LCFF_X20_Y4_N17; Fanout = 2; REG Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]~32 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.201 ns ( 27.87 % ) " "Info: Total cell delay = 2.201 ns ( 27.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.695 ns ( 72.13 % ) " "Info: Total interconnect delay = 5.695 ns ( 72.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.896 ns" { pin_in[1] add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1]~41 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2]~42 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3]~43 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4]~44 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5]~45 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]~46 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]~32 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.896 ns" { pin_in[1] pin_in[1]~combout add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1]~41 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2]~42 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3]~43 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4]~44 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5]~45 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]~46 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]~32 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } { 0.000ns 0.000ns 5.695ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.850ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.410ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.358 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.358 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 248 104 272 264 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 248 104 272 264 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.710 ns) + CELL(0.537 ns) 2.358 ns add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\] 3 REG LCFF_X20_Y4_N17 2 " "Info: 3: + IC(0.710 ns) + CELL(0.537 ns) = 2.358 ns; Loc. = LCFF_X20_Y4_N17; Fanout = 2; REG Node = 'add_sub:inst\|lpm_add_sub:lpm_add_sub_component\|add_sub_blg:auto_generated\|pipeline_dffe\[7\]'" {  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.247 ns" { clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } "NODE_NAME" } } { "db/add_sub_blg.tdf" "" { Text "D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf" 30 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.72 % ) " "Info: Total cell delay = 1.526 ns ( 64.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.832 ns ( 35.28 % ) " "Info: Total interconnect delay = 0.832 ns ( 35.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.358 ns" { clk clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.358 ns" { clk clk~combout clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } { 0.000ns 0.000ns 0.122ns 0.710ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.896 ns" { pin_in[1] add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1]~41 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2]~42 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3]~43 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4]~44 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5]~45 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]~46 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]~32 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "7.896 ns" { pin_in[1] pin_in[1]~combout add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1]~41 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2]~42 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3]~43 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4]~44 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5]~45 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]~46 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]~32 add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } { 0.000ns 0.000ns 5.695ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.850ns 0.414ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.410ns 0.084ns } "" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.358 ns" { clk clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.358 ns" { clk clk~combout clk~clkctrl add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] } { 0.000ns 0.000ns 0.122ns 0.710ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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