dds.fit.qmsg

基于CYCLONE II的程序,DDS原理的函数信号发生器.采用查表法实现.各位可以参考.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Web Edition " "Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed May 23 19:46:53 2007 " "Info: Processing started: Wed May 23 19:46:53 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DDS -c dds " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DDS -c dds" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "dds EP2C5T144C6 " "Info: Automatically selected device EP2C5T144C6 for design dds" {  } {  } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0}
{ "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_TOP" "1 0 " "Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use" { { "Info" "IFITCC_FITCC_QID_PARTITION_BACK_ANNOTATION_NONE_OVERRIDE" "33 Top " "Info: Previous placement does not exist for 33 of 33 atoms in partition Top" {  } {  } 0 0 "Previous placement does not exist for %1!d! of %1!d! atoms in partition %2!s!" 0 0}  } {  } 0 0 "The Fitter has identified %1!d! logical partitions of which %2!d! have a previous placement to use" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C8T144C6 " "Info: Device EP2C8T144C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ 1 " "Info: Pin ~ASDO~ is reserved at location 1" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ 2 " "Info: Pin ~nCSO~ is reserved at location 2" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS41p/nCEO~ 76 " "Info: Pin ~LVDS41p/nCEO~ is reserved at location 76" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "17 17 " "Warning: No exact pin location assignment(s) for 17 pins of 17 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_out\[7\] " "Info: Pin pin_out\[7\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 320 528 704 336 "pin_out\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[7] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_out\[6\] " "Info: Pin pin_out\[6\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 320 528 704 336 "pin_out\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[6] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_out\[5\] " "Info: Pin pin_out\[5\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 320 528 704 336 "pin_out\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[5] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_out\[4\] " "Info: Pin pin_out\[4\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 320 528 704 336 "pin_out\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[4] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_out\[3\] " "Info: Pin pin_out\[3\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 320 528 704 336 "pin_out\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[3] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_out\[2\] " "Info: Pin pin_out\[2\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 320 528 704 336 "pin_out\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[2] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_out\[1\] " "Info: Pin pin_out\[1\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 320 528 704 336 "pin_out\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[1] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_out\[0\] " "Info: Pin pin_out\[0\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 320 528 704 336 "pin_out\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[0] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_out[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 248 104 272 264 "clk" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_in\[7\] " "Info: Pin pin_in\[7\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 352 120 288 368 "pin_in\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[7] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_in\[6\] " "Info: Pin pin_in\[6\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 352 120 288 368 "pin_in\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[6] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_in\[5\] " "Info: Pin pin_in\[5\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 352 120 288 368 "pin_in\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[5] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_in\[4\] " "Info: Pin pin_in\[4\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 352 120 288 368 "pin_in\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[4] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_in\[3\] " "Info: Pin pin_in\[3\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 352 120 288 368 "pin_in\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[3] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_in\[2\] " "Info: Pin pin_in\[2\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 352 120 288 368 "pin_in\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[2] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_in\[1\] " "Info: Pin pin_in\[1\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 352 120 288 368 "pin_in\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[1] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "pin_in\[0\] " "Info: Pin pin_in\[0\] not assigned to an exact location on the device" {  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 352 120 288 368 "pin_in\[7..0\]" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[0] } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pin_in[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN 17 (CLK0, LVDSCLK0p, Input)) " "Info: Automatically promoted node clk (placed in PIN 17 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0}  } { { "test.bdf" "" { Schematic "D:/works/模电/lab/VHDL/dds/test.bdf" { { 248 104 272 264 "clk" "" } } } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}