dds.tan.rpt

基于CYCLONE II的程序,DDS原理的函数信号发生器.采用查表法实现.各位可以参考.

        Info: + Longest register to register delay is 1.708 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y4_N3; Fanout = 3; REG Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]'
            Info: 2: + IC(0.307 ns) + CELL(0.393 ns) = 0.700 ns; Loc. = LCCOMB_X20_Y4_N2; Fanout = 2; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]~40'
            Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.771 ns; Loc. = LCCOMB_X20_Y4_N4; Fanout = 2; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1]~41'
            Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.842 ns; Loc. = LCCOMB_X20_Y4_N6; Fanout = 2; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2]~42'
            Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 0.913 ns; Loc. = LCCOMB_X20_Y4_N8; Fanout = 2; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3]~43'
            Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 0.984 ns; Loc. = LCCOMB_X20_Y4_N10; Fanout = 2; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4]~44'
            Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.055 ns; Loc. = LCCOMB_X20_Y4_N12; Fanout = 2; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5]~45'
            Info: 8: + IC(0.000 ns) + CELL(0.159 ns) = 1.214 ns; Loc. = LCCOMB_X20_Y4_N14; Fanout = 1; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]~46'
            Info: 9: + IC(0.000 ns) + CELL(0.410 ns) = 1.624 ns; Loc. = LCCOMB_X20_Y4_N16; Fanout = 1; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]~32'
            Info: 10: + IC(0.000 ns) + CELL(0.084 ns) = 1.708 ns; Loc. = LCFF_X20_Y4_N17; Fanout = 2; REG Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]'
            Info: Total cell delay = 1.401 ns ( 82.03 % )
            Info: Total interconnect delay = 0.307 ns ( 17.97 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.358 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.710 ns) + CELL(0.537 ns) = 2.358 ns; Loc. = LCFF_X20_Y4_N17; Fanout = 2; REG Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]'
                Info: Total cell delay = 1.526 ns ( 64.72 % )
                Info: Total interconnect delay = 0.832 ns ( 35.28 % )
            Info: - Longest clock path from clock "clk" to source register is 2.358 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.710 ns) + CELL(0.537 ns) = 2.358 ns; Loc. = LCFF_X20_Y4_N3; Fanout = 3; REG Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]'
                Info: Total cell delay = 1.526 ns ( 64.72 % )
                Info: Total interconnect delay = 0.832 ns ( 35.28 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]" (data pin = "pin_in[1]", clock pin = "clk") is 5.502 ns
    Info: + Longest pin to register delay is 7.896 ns
        Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_113; Fanout = 2; PIN Node = 'pin_in[1]'
        Info: 2: + IC(5.695 ns) + CELL(0.414 ns) = 6.959 ns; Loc. = LCCOMB_X20_Y4_N4; Fanout = 2; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1]~41'
        Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 7.030 ns; Loc. = LCCOMB_X20_Y4_N6; Fanout = 2; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2]~42'
        Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 7.101 ns; Loc. = LCCOMB_X20_Y4_N8; Fanout = 2; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3]~43'
        Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 7.172 ns; Loc. = LCCOMB_X20_Y4_N10; Fanout = 2; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4]~44'
        Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 7.243 ns; Loc. = LCCOMB_X20_Y4_N12; Fanout = 2; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5]~45'
        Info: 7: + IC(0.000 ns) + CELL(0.159 ns) = 7.402 ns; Loc. = LCCOMB_X20_Y4_N14; Fanout = 1; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]~46'
        Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 7.812 ns; Loc. = LCCOMB_X20_Y4_N16; Fanout = 1; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]~32'
        Info: 9: + IC(0.000 ns) + CELL(0.084 ns) = 7.896 ns; Loc. = LCFF_X20_Y4_N17; Fanout = 2; REG Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]'
        Info: Total cell delay = 2.201 ns ( 27.87 % )
        Info: Total interconnect delay = 5.695 ns ( 72.13 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.358 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.710 ns) + CELL(0.537 ns) = 2.358 ns; Loc. = LCFF_X20_Y4_N17; Fanout = 2; REG Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]'
        Info: Total cell delay = 1.526 ns ( 64.72 % )
        Info: Total interconnect delay = 0.832 ns ( 35.28 % )
Info: tco from clock "clk" to destination pin "pin_out[6]" through register "add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]" is 6.969 ns
    Info: + Longest clock path from clock "clk" to source register is 2.358 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.710 ns) + CELL(0.537 ns) = 2.358 ns; Loc. = LCFF_X20_Y4_N15; Fanout = 3; REG Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]'
        Info: Total cell delay = 1.526 ns ( 64.72 % )
        Info: Total interconnect delay = 0.832 ns ( 35.28 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 4.361 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y4_N15; Fanout = 3; REG Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6]'
        Info: 2: + IC(1.573 ns) + CELL(2.788 ns) = 4.361 ns; Loc. = PIN_126; Fanout = 0; PIN Node = 'pin_out[6]'
        Info: Total cell delay = 2.788 ns ( 63.93 % )
        Info: Total interconnect delay = 1.573 ns ( 36.07 % )
Info: th for register "add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]" (data pin = "pin_in[0]", clock pin = "clk") is 0.066 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.358 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.710 ns) + CELL(0.537 ns) = 2.358 ns; Loc. = LCFF_X20_Y4_N3; Fanout = 3; REG Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]'
        Info: Total cell delay = 1.526 ns ( 64.72 % )
        Info: Total interconnect delay = 0.832 ns ( 35.28 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 2.558 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_88; Fanout = 2; PIN Node = 'pin_in[0]'
        Info: 2: + IC(1.038 ns) + CELL(0.437 ns) = 2.474 ns; Loc. = LCCOMB_X20_Y4_N2; Fanout = 1; COMB Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]~39'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.558 ns; Loc. = LCFF_X20_Y4_N3; Fanout = 3; REG Node = 'add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]'
        Info: Total cell delay = 1.520 ns ( 59.42 % )
        Info: Total interconnect delay = 1.038 ns ( 40.58 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 100 megabytes of memory during processing
    Info: Processing ended: Wed May 23 19:47:05 2007
    Info: Elapsed time: 00:00:00