dds.tan.rpt

基于CYCLONE II的程序,DDS原理的函数信号发生器.采用查表法实现.各位可以参考.

; N/A   ; None         ; 0.906 ns   ; pin_in[0] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] ; clk      ;
; N/A   ; None         ; 0.835 ns   ; pin_in[0] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5] ; clk      ;
; N/A   ; None         ; 0.764 ns   ; pin_in[0] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4] ; clk      ;
; N/A   ; None         ; 0.693 ns   ; pin_in[0] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3] ; clk      ;
; N/A   ; None         ; 0.622 ns   ; pin_in[0] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2] ; clk      ;
; N/A   ; None         ; 0.551 ns   ; pin_in[0] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1] ; clk      ;
; N/A   ; None         ; 0.164 ns   ; pin_in[0] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] ; clk      ;
+-------+--------------+------------+-----------+--------------------------------------------------------------------------------------------+----------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                                      ;
+-------+--------------+------------+--------------------------------------------------------------------------------------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From                                                                                       ; To         ; From Clock ;
+-------+--------------+------------+--------------------------------------------------------------------------------------------+------------+------------+
; N/A   ; None         ; 6.969 ns   ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] ; pin_out[6] ; clk        ;
; N/A   ; None         ; 6.713 ns   ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5] ; pin_out[5] ; clk        ;
; N/A   ; None         ; 6.693 ns   ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3] ; pin_out[3] ; clk        ;
; N/A   ; None         ; 6.515 ns   ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2] ; pin_out[2] ; clk        ;
; N/A   ; None         ; 6.375 ns   ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1] ; pin_out[1] ; clk        ;
; N/A   ; None         ; 6.368 ns   ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] ; pin_out[7] ; clk        ;
; N/A   ; None         ; 6.356 ns   ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] ; pin_out[0] ; clk        ;
; N/A   ; None         ; 6.122 ns   ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4] ; pin_out[4] ; clk        ;
+-------+--------------+------------+--------------------------------------------------------------------------------------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                                          ;
+---------------+-------------+-----------+-----------+--------------------------------------------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To                                                                                         ; To Clock ;
+---------------+-------------+-----------+-----------+--------------------------------------------------------------------------------------------+----------+
; N/A           ; None        ; 0.066 ns  ; pin_in[0] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0] ; clk      ;
; N/A           ; None        ; -0.321 ns ; pin_in[0] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1] ; clk      ;
; N/A           ; None        ; -0.392 ns ; pin_in[0] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2] ; clk      ;
; N/A           ; None        ; -0.463 ns ; pin_in[0] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3] ; clk      ;
; N/A           ; None        ; -0.534 ns ; pin_in[0] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4] ; clk      ;
; N/A           ; None        ; -0.605 ns ; pin_in[0] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5] ; clk      ;
; N/A           ; None        ; -0.676 ns ; pin_in[0] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] ; clk      ;
; N/A           ; None        ; -0.835 ns ; pin_in[0] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] ; clk      ;
; N/A           ; None        ; -3.572 ns ; pin_in[5] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5] ; clk      ;
; N/A           ; None        ; -3.684 ns ; pin_in[7] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] ; clk      ;
; N/A           ; None        ; -3.813 ns ; pin_in[2] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2] ; clk      ;
; N/A           ; None        ; -3.880 ns ; pin_in[4] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4] ; clk      ;
; N/A           ; None        ; -3.956 ns ; pin_in[6] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] ; clk      ;
; N/A           ; None        ; -3.959 ns ; pin_in[5] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] ; clk      ;
; N/A           ; None        ; -4.118 ns ; pin_in[5] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] ; clk      ;
; N/A           ; None        ; -4.196 ns ; pin_in[2] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3] ; clk      ;
; N/A           ; None        ; -4.263 ns ; pin_in[4] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5] ; clk      ;
; N/A           ; None        ; -4.267 ns ; pin_in[2] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4] ; clk      ;
; N/A           ; None        ; -4.314 ns ; pin_in[3] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3] ; clk      ;
; N/A           ; None        ; -4.334 ns ; pin_in[4] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] ; clk      ;
; N/A           ; None        ; -4.338 ns ; pin_in[2] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5] ; clk      ;
; N/A           ; None        ; -4.409 ns ; pin_in[2] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] ; clk      ;
; N/A           ; None        ; -4.432 ns ; pin_in[6] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] ; clk      ;
; N/A           ; None        ; -4.443 ns ; pin_in[1] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[1] ; clk      ;
; N/A           ; None        ; -4.493 ns ; pin_in[4] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] ; clk      ;
; N/A           ; None        ; -4.568 ns ; pin_in[2] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] ; clk      ;
; N/A           ; None        ; -4.700 ns ; pin_in[3] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4] ; clk      ;
; N/A           ; None        ; -4.771 ns ; pin_in[3] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5] ; clk      ;
; N/A           ; None        ; -4.829 ns ; pin_in[1] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[2] ; clk      ;
; N/A           ; None        ; -4.842 ns ; pin_in[3] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] ; clk      ;
; N/A           ; None        ; -4.900 ns ; pin_in[1] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[3] ; clk      ;
; N/A           ; None        ; -4.971 ns ; pin_in[1] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[4] ; clk      ;
; N/A           ; None        ; -5.001 ns ; pin_in[3] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] ; clk      ;
; N/A           ; None        ; -5.042 ns ; pin_in[1] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[5] ; clk      ;
; N/A           ; None        ; -5.113 ns ; pin_in[1] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[6] ; clk      ;
; N/A           ; None        ; -5.272 ns ; pin_in[1] ; add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7] ; clk      ;
+---------------+-------------+-----------+-----------+--------------------------------------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition
    Info: Processing started: Wed May 23 19:47:05 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DDS -c dds --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[0]" and destination register "add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated|pipeline_dffe[7]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.