📄 dds.map.rpt
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; look_add.inc ; yes ; Megafunction ; e:/altera/61/quartus/libraries/megafunctions/look_add.inc ;
; bypassff.inc ; yes ; Megafunction ; e:/altera/61/quartus/libraries/megafunctions/bypassff.inc ;
; altshift.inc ; yes ; Megafunction ; e:/altera/61/quartus/libraries/megafunctions/altshift.inc ;
; alt_stratix_add_sub.inc ; yes ; Megafunction ; e:/altera/61/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc ; yes ; Megafunction ; e:/altera/61/quartus/libraries/megafunctions/alt_mercury_add_sub.inc ;
; aglobal61.inc ; yes ; Megafunction ; e:/altera/61/quartus/libraries/megafunctions/aglobal61.inc ;
; db/add_sub_blg.tdf ; yes ; Auto-Generated Megafunction ; D:/works/模电/lab/VHDL/dds/db/add_sub_blg.tdf ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements ; 8 ;
; ; ;
; Total combinational functions ; 8 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 0 ;
; -- 3 input functions ; 7 ;
; -- <=2 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 1 ;
; -- arithmetic mode ; 7 ;
; ; ;
; Total registers ; 8 ;
; -- Dedicated logic registers ; 8 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 0 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 8 ;
; Total fan-out ; 47 ;
; Average fan-out ; 1.42 ;
+---------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------+
; |test ; 8 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test ;
; |add_sub:inst| ; 8 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test|add_sub:inst ;
; |lpm_add_sub:lpm_add_sub_component| ; 8 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test|add_sub:inst|lpm_add_sub:lpm_add_sub_component ;
; |add_sub_blg:auto_generated| ; 8 (8) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test|add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 8 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: add_sub:inst|lpm_add_sub:lpm_add_sub_component ;
+------------------------+-------------+------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+------------------------------------------------------+
; LPM_WIDTH ; 8 ; Signed Integer ;
; LPM_REPRESENTATION ; SIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ;
; LPM_PIPELINE ; 1 ; Signed Integer ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; Cyclone II ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_blg ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition
Info: Processing started: Wed May 23 19:46:49 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDS -c dds
Info: Found 1 design units, including 1 entities, in source file test.bdf
Info: Found entity 1: test
Info: Elaborating entity "test" for the top level hierarchy
Warning: Using design file add_sub.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: add_sub-SYN
Info: Found entity 1: add_sub
Info: Elaborating entity "add_sub" for hierarchy "add_sub:inst"
Info: Found 1 design units, including 1 entities, in source file e:/altera/61/quartus/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Elaborating entity "lpm_add_sub" for hierarchy "add_sub:inst|lpm_add_sub:lpm_add_sub_component"
Info: Elaborated megafunction instantiation "add_sub:inst|lpm_add_sub:lpm_add_sub_component"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_blg.tdf
Info: Found entity 1: add_sub_blg
Info: Elaborating entity "add_sub_blg" for hierarchy "add_sub:inst|lpm_add_sub:lpm_add_sub_component|add_sub_blg:auto_generated"
Info: Implemented 25 device resources after synthesis - the final resource count might be different
Info: Implemented 9 input pins
Info: Implemented 8 output pins
Info: Implemented 8 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Allocated 137 megabytes of memory during processing
Info: Processing ended: Wed May 23 19:46:51 2007
Info: Elapsed time: 00:00:02
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