fifo_1.sim.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

; Display complete 1/0 value coverage report                                                 ; On         ; On            ;
; Display missing 1-value coverage report                                                    ; On         ; On            ;
; Display missing 0-value coverage report                                                    ; On         ; On            ;
; Detect setup and hold time violations                                                      ; Off        ; Off           ;
; Detect glitches                                                                            ; Off        ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off        ; Off           ;
; Generate Signal Activity File                                                              ; Off        ; Off           ;
; Generate VCD File for PowerPlay Power Analyzer                                             ; Off        ; Off           ;
; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; On         ;               ;
; Glitch Filtering                                                                           ; Off        ; Off           ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|dpram_0it:FIFOram|altsyncram_urj1:altsyncram2|ALTSYNCRAM ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      74.70 % ;
; Total nodes checked                                 ; 77           ;
; Total output ports checked                          ; 83           ;
; Total output ports with complete 1/0-value coverage ; 62           ;
; Total output ports with no 1/0-value coverage       ; 15           ;
; Total output ports with no 1-value coverage         ; 19           ;
; Total output ports with no 0-value coverage         ; 17           ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                                                                                                                             ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                                                                       ; Output Port Name                                                                                                                                                   ; Output Port Type ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; |FIFO_1|full                                                                                                                                                    ; |FIFO_1|full                                                                                                                                                       ; pin_out          ;
; |FIFO_1|rd                                                                                                                                                      ; |FIFO_1|rd                                                                                                                                                         ; out              ;
; |FIFO_1|clk                                                                                                                                                     ; |FIFO_1|clk                                                                                                                                                        ; out              ;
; |FIFO_1|din[3]                                                                                                                                                  ; |FIFO_1|din[3]                                                                                                                                                     ; out              ;
; |FIFO_1|din[2]                                                                                                                                                  ; |FIFO_1|din[2]                                                                                                                                                     ; out              ;
; |FIFO_1|din[1]                                                                                                                                                  ; |FIFO_1|din[1]                                                                                                                                                     ; out              ;
; |FIFO_1|empty                                                                                                                                                   ; |FIFO_1|empty                                                                                                                                                      ; pin_out          ;
; |FIFO_1|dout[2]                                                                                                                                                 ; |FIFO_1|dout[2]                                                                                                                                                    ; pin_out          ;
; |FIFO_1|dout[1]                                                                                                                                                 ; |FIFO_1|dout[1]                                                                                                                                                    ; pin_out          ;
; |FIFO_1|usdw[2]                                                                                                                                                 ; |FIFO_1|usdw[2]                                                                                                                                                    ; pin_out          ;
; |FIFO_1|usdw[1]                                                                                                                                                 ; |FIFO_1|usdw[1]                                                                                                                                                    ; pin_out          ;
; |FIFO_1|usdw[0]                                                                                                                                                 ; |FIFO_1|usdw[0]                                                                                                                                                    ; pin_out          ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|valid_rreq                                                        ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|valid_rreq                                                           ; out0             ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|counter_comb_bita0                                ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|counter_comb_bita0                                   ; combout          ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|counter_comb_bita0                                ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|counter_comb_bita0~COUT                              ; cout             ;
; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|counter_comb_bita1                                ; |FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr|counter_comb_bita1                                   ; combout          ;