a_dpfifo_3iv.tdf

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

--a_dpfifo ADD_RAM_OUTPUT_REGISTER="OFF" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone II" LPM_NUMWORDS=8 LPM_SHOWAHEAD="OFF" lpm_width=8 lpm_widthu=3 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" clock data empty full q rreq sclr wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 7.0 cbx_altdpram 2006:11:03:15:22:16:SJ cbx_altsyncram 2007:01:25:14:36:16:SJ cbx_cycloneii 2006:09:29:19:03:26:SJ cbx_fifo_common 2006:03:14:10:59:42:SJ cbx_lpm_add_sub 2006:10:10:22:03:24:SJ cbx_lpm_compare 2006:04:25:14:54:12:SJ cbx_lpm_counter 2006:11:07:16:43:46:SJ cbx_lpm_decode 2006:04:25:15:10:18:SJ cbx_lpm_mux 2006:04:25:15:10:08:SJ cbx_mgl 2006:10:27:16:08:48:SJ cbx_scfifo 2006:10:16:20:17:00:SJ cbx_stratix 2006:09:18:10:47:42:SJ cbx_stratixii 2006:10:13:14:01:30:SJ cbx_stratixiii 2006:10:19:19:28:28:SJ cbx_util_mgl 2006:11:03:10:32:30:SJ  VERSION_END


--  Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION a_fefifo_n4e (aclr, clock, rreq, sclr, wreq)
RETURNS ( empty, full);
FUNCTION dpram_0it (data[7..0], inclock, outclock, outclocken, rdaddress[2..0], wraddress[2..0], wren)
RETURNS ( q[7..0]);
FUNCTION cntr_cjb (aclr, clock, cnt_en, sclr)
RETURNS ( q[2..0]);

--synthesis_resources = lut 6 M4K 1 reg 8 
SUBDESIGN a_dpfifo_3iv
( 
	clock	:	input;
	data[7..0]	:	input;
	empty	:	output;
	full	:	output;
	q[7..0]	:	output;
	rreq	:	input;
	sclr	:	input;
	wreq	:	input;
) 
VARIABLE 
	fifo_state : a_fefifo_n4e;
	FIFOram : dpram_0it;
	rd_ptr_count : cntr_cjb;
	wr_ptr : cntr_cjb;
	aclr	: NODE;
	rd_ptr[2..0]	: WIRE;
	valid_rreq	: WIRE;
	valid_wreq	: WIRE;

BEGIN 
	fifo_state.aclr = aclr;
	fifo_state.clock = clock;
	fifo_state.rreq = rreq;
	fifo_state.sclr = sclr;
	fifo_state.wreq = wreq;
	FIFOram.data[] = data[];
	FIFOram.inclock = clock;
	FIFOram.outclock = clock;
	FIFOram.outclocken = (valid_rreq # sclr);
	FIFOram.rdaddress[] = ((! sclr) & rd_ptr[]);
	FIFOram.wraddress[] = wr_ptr.q[];
	FIFOram.wren = valid_wreq;
	rd_ptr_count.aclr = aclr;
	rd_ptr_count.clock = clock;
	rd_ptr_count.cnt_en = valid_rreq;
	rd_ptr_count.sclr = sclr;
	wr_ptr.aclr = aclr;
	wr_ptr.clock = clock;
	wr_ptr.cnt_en = valid_wreq;
	wr_ptr.sclr = sclr;
	aclr = GND;
	empty = fifo_state.empty;
	full = fifo_state.full;
	q[] = FIFOram.q[];
	rd_ptr[] = rd_ptr_count.q[];
	valid_rreq = (rreq & (! fifo_state.empty));
	valid_wreq = (wreq & (! fifo_state.full));
END;
--VALID FILE