yxbianma8_3.hier_info

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

|yxbianma8_3
i[0] => comb~16.DATAA
i[0] => comb~3.DATAA
i[0] => comb~10.IN0
i[0] => Equal0.IN7
i[1] => comb~25.DATAA
i[1] => comb~3.OUTPUTSELECT
i[1] => comb~16.OUTPUTSELECT
i[1] => comb~40.IN0
i[1] => Equal0.IN6
i[2] => comb~33.DATAA
i[2] => comb~2.OUTPUTSELECT
i[2] => comb~17.OUTPUTSELECT
i[2] => comb~25.OUTPUTSELECT
i[2] => comb~41.IN0
i[2] => Equal0.IN5
i[3] => comb~1.OUTPUTSELECT
i[3] => comb~18.OUTPUTSELECT
i[3] => comb~26.OUTPUTSELECT
i[3] => comb~33.OUTPUTSELECT
i[3] => comb~42.IN0
i[3] => Equal0.IN4
i[4] => comb~45.DATAA
i[4] => comb~0.OUTPUTSELECT
i[4] => comb~19.OUTPUTSELECT
i[4] => comb~27.OUTPUTSELECT
i[4] => comb~34.OUTPUTSELECT
i[4] => comb~43.IN0
i[4] => Equal0.IN3
i[5] => comb~11.OUTPUTSELECT
i[5] => comb~20.OUTPUTSELECT
i[5] => comb~28.OUTPUTSELECT
i[5] => comb~35.OUTPUTSELECT
i[5] => comb~44.IN0
i[5] => comb~45.OUTPUTSELECT
i[5] => Equal0.IN2
i[6] => comb~12.OUTPUTSELECT
i[6] => comb~21.OUTPUTSELECT
i[6] => comb~29.OUTPUTSELECT
i[6] => comb~36.OUTPUTSELECT
i[6] => comb~46.IN0
i[6] => comb~47.OUTPUTSELECT
i[6] => Equal0.IN1
i[7] => comb~13.OUTPUTSELECT
i[7] => comb~22.OUTPUTSELECT
i[7] => comb~30.OUTPUTSELECT
i[7] => comb~37.OUTPUTSELECT
i[7] => comb~48.IN0
i[7] => comb~49.OUTPUTSELECT
i[7] => Equal0.IN0
ei => comb~14.OUTPUTSELECT
ei => comb~23.OUTPUTSELECT
ei => comb~31.OUTPUTSELECT
ei => comb~38.OUTPUTSELECT
ei => comb~50.IN0
ei => comb~51.OUTPUTSELECT
y[0] <= y[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
y[1] <= y[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
y[2] <= y[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
eo <= eo$latch.DB_MAX_OUTPUT_PORT_TYPE
gs <= gs$latch.DB_MAX_OUTPUT_PORT_TYPE