yxbianma8_3.vhd

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

library ieee;
use ieee.std_logic_1164.all;
entity yxbianma8_3 is
port(i:in std_logic_vector(7 downto 0);
     ei:in std_logic;
     y:out std_logic_vector(2 downto 0);
     eo,gs:out std_logic);
end;
architecture one of yxbianma8_3 is
begin
process(i,ei)
begin
if ei='1' then 
	y<="111";
	gs<='1';
	eo<='1';
else
	if i(7)='0' then
		y<="000";
		gs<='0';
		eo<='1';
	elsif i(6)='0' then
		y<="001";
		gs<='0';
		eo<='1';
	elsif i(5)='0' then
		y<="010";
		gs<='0';
		eo<='1';
	elsif i(4)='0' then
		y<="011";
		gs<='0';
		eo<='1';
	elsif i(3)='0' then
		y<="100";
		gs<='0';
		eo<='1';
	elsif i(2)='0' then
		y<="101";
		gs<='0';
		eo<='1';
	elsif i(1)='0' then
		y<="110";
		gs<='0';
		eo<='1';
	elsif i(0)='0' then
		y<="111";
		gs<='0';
		eo<='1';
	elsif i="11111111" then
		y<="111";
		gs<='1';
		eo<='0';
	end if;
end if;
end process;
end;