sub4.tan.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 07 16:07:35 2007 " "Info: Processing started: Wed Mar 07 16:07:35 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off sub4 -c sub4 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sub4 -c sub4 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "ci dout\[2\] 16.540 ns Longest " "Info: Longest tpd from source pin \"ci\" to destination pin \"dout\[2\]\" is 16.540 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.934 ns) 0.934 ns ci 1 PIN PIN_67 1 " "Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_67; Fanout = 1; PIN Node = 'ci'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "" { ci } "NODE_NAME" } } { "sub4.vhd" "" { Text "D:/my_eda/sub4/sub4.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.814 ns) + CELL(0.706 ns) 8.454 ns Add0~19 2 COMB LCCOMB_X33_Y10_N14 2 " "Info: 2: + IC(6.814 ns) + CELL(0.706 ns) = 8.454 ns; Loc. = LCCOMB_X33_Y10_N14; Fanout = 2; COMB Node = 'Add0~19'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.520 ns" { ci Add0~19 } "NODE_NAME" } } { "e:/altera60/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera60/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.540 ns Add0~21 3 COMB LCCOMB_X33_Y10_N16 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 8.540 ns; Loc. = LCCOMB_X33_Y10_N16; Fanout = 2; COMB Node = 'Add0~21'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~19 Add0~21 } "NODE_NAME" } } { "e:/altera60/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera60/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.626 ns Add0~23 4 COMB LCCOMB_X33_Y10_N18 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 8.626 ns; Loc. = LCCOMB_X33_Y10_N18; Fanout = 2; COMB Node = 'Add0~23'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~21 Add0~23 } "NODE_NAME" } } { "e:/altera60/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera60/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 9.132 ns Add0~24 5 COMB LCCOMB_X33_Y10_N20 1 " "Info: 5: + IC(0.000 ns) + CELL(0.506 ns) = 9.132 ns; Loc. = LCCOMB_X33_Y10_N20; Fanout = 1; COMB Node = 'Add0~24'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "0.506 ns" { Add0~23 Add0~24 } "NODE_NAME" } } { "e:/altera60/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera60/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.352 ns) + CELL(3.056 ns) 16.540 ns dout\[2\] 6 PIN PIN_24 0 " "Info: 6: + IC(4.352 ns) + CELL(3.056 ns) = 16.540 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'dout\[2\]'" {  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "7.408 ns" { Add0~24 dout[2] } "NODE_NAME" } } { "sub4.vhd" "" { Text "D:/my_eda/sub4/sub4.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.374 ns ( 32.49 % ) " "Info: Total cell delay = 5.374 ns ( 32.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.166 ns ( 67.51 % ) " "Info: Total interconnect delay = 11.166 ns ( 67.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera60/quartus60/win/TimingClosureFloorplan.fld" "" "16.540 ns" { ci Add0~19 Add0~21 Add0~23 Add0~24 dout[2] } "NODE_NAME" } } { "e:/altera60/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera60/quartus60/win/Technology_Viewer.qrui" "16.540 ns" { ci ci~combout Add0~19 Add0~21 Add0~23 Add0~24 dout[2] } { 0.000ns 0.000ns 6.814ns 0.000ns 0.000ns 0.000ns 4.352ns } { 0.000ns 0.934ns 0.706ns 0.086ns 0.086ns 0.506ns 3.056ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 07 16:07:35 2007 " "Info: Processing ended: Wed Mar 07 16:07:35 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}