📄 sub4.tan.rpt
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Timing Analyzer report for sub4
Wed Mar 07 16:07:35 2007
Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+---------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+---------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 16.540 ns ; ci ; dout[2] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+---------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C8T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+--------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+---------+
; N/A ; None ; 16.540 ns ; ci ; dout[2] ;
; N/A ; None ; 15.919 ns ; b[0] ; dout[2] ;
; N/A ; None ; 15.862 ns ; ci ; dout[3] ;
; N/A ; None ; 15.746 ns ; b[1] ; dout[2] ;
; N/A ; None ; 15.686 ns ; a[1] ; dout[2] ;
; N/A ; None ; 15.241 ns ; b[0] ; dout[3] ;
; N/A ; None ; 15.211 ns ; a[0] ; dout[2] ;
; N/A ; None ; 15.068 ns ; b[1] ; dout[3] ;
; N/A ; None ; 15.008 ns ; a[1] ; dout[3] ;
; N/A ; None ; 14.533 ns ; a[0] ; dout[3] ;
; N/A ; None ; 13.932 ns ; ci ; dout[0] ;
; N/A ; None ; 13.357 ns ; ci ; cout ;
; N/A ; None ; 13.146 ns ; ci ; dout[1] ;
; N/A ; None ; 12.921 ns ; b[0] ; dout[0] ;
; N/A ; None ; 12.736 ns ; b[0] ; cout ;
; N/A ; None ; 12.563 ns ; b[1] ; cout ;
; N/A ; None ; 12.525 ns ; b[0] ; dout[1] ;
; N/A ; None ; 12.503 ns ; a[1] ; cout ;
; N/A ; None ; 12.210 ns ; a[0] ; dout[0] ;
; N/A ; None ; 12.028 ns ; a[0] ; cout ;
; N/A ; None ; 11.959 ns ; b[1] ; dout[1] ;
; N/A ; None ; 11.902 ns ; a[1] ; dout[1] ;
; N/A ; None ; 11.817 ns ; a[0] ; dout[1] ;
; N/A ; None ; 9.746 ns ; a[2] ; dout[2] ;
; N/A ; None ; 9.612 ns ; b[2] ; dout[2] ;
; N/A ; None ; 9.463 ns ; a[2] ; dout[3] ;
; N/A ; None ; 9.327 ns ; b[2] ; dout[3] ;
; N/A ; None ; 8.992 ns ; b[3] ; dout[3] ;
; N/A ; None ; 8.937 ns ; a[3] ; dout[3] ;
; N/A ; None ; 6.958 ns ; a[2] ; cout ;
; N/A ; None ; 6.882 ns ; b[3] ; cout ;
; N/A ; None ; 6.825 ns ; a[3] ; cout ;
; N/A ; None ; 6.822 ns ; b[2] ; cout ;
+-------+-------------------+-----------------+------+---------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
Info: Processing started: Wed Mar 07 16:07:35 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sub4 -c sub4 --timing_analysis_only
Info: Longest tpd from source pin "ci" to destination pin "dout[2]" is 16.540 ns
Info: 1: + IC(0.000 ns) + CELL(0.934 ns) = 0.934 ns; Loc. = PIN_67; Fanout = 1; PIN Node = 'ci'
Info: 2: + IC(6.814 ns) + CELL(0.706 ns) = 8.454 ns; Loc. = LCCOMB_X33_Y10_N14; Fanout = 2; COMB Node = 'Add0~19'
Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 8.540 ns; Loc. = LCCOMB_X33_Y10_N16; Fanout = 2; COMB Node = 'Add0~21'
Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 8.626 ns; Loc. = LCCOMB_X33_Y10_N18; Fanout = 2; COMB Node = 'Add0~23'
Info: 5: + IC(0.000 ns) + CELL(0.506 ns) = 9.132 ns; Loc. = LCCOMB_X33_Y10_N20; Fanout = 1; COMB Node = 'Add0~24'
Info: 6: + IC(4.352 ns) + CELL(3.056 ns) = 16.540 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 'dout[2]'
Info: Total cell delay = 5.374 ns ( 32.49 % )
Info: Total interconnect delay = 11.166 ns ( 67.51 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Wed Mar 07 16:07:35 2007
Info: Elapsed time: 00:00:02
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