bianma8_3.map.summary

来自「基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Thu May 31 15:58:15 2007
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : bianma8_3
Top-level Entity Name : bianma8_3
Family : Cyclone II
Total logic elements : 8
    Total combinational functions : 8
    Dedicated logic registers : 0
Total registers : 0
Total pins : 11
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0