add4.tan.qmsg

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 13 11:03:55 2007 " "Info: Processing started: Sun May 13 11:03:55 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off add4 -c add4 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off add4 -c add4 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[0\] s\[2\] 15.741 ns Longest " "Info: Longest tpd from source pin \"a\[0\]\" to destination pin \"s\[2\]\" is 15.741 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.945 ns) 0.945 ns a\[0\] 1 PIN PIN_25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.945 ns) = 0.945 ns; Loc. = PIN_25; Fanout = 2; PIN Node = 'a\[0\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[0] } "NODE_NAME" } } { "add4.vhd" "" { Text "D:/my_eda/add4/add4.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.764 ns) + CELL(0.596 ns) 8.305 ns Add0~15 2 COMB LCCOMB_X33_Y8_N16 2 " "Info: 2: + IC(6.764 ns) + CELL(0.596 ns) = 8.305 ns; Loc. = LCCOMB_X33_Y8_N16; Fanout = 2; COMB Node = 'Add0~15'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.360 ns" { a[0] Add0~15 } "NODE_NAME" } } { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 8.391 ns Add0~17 3 COMB LCCOMB_X33_Y8_N18 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 8.391 ns; Loc. = LCCOMB_X33_Y8_N18; Fanout = 2; COMB Node = 'Add0~17'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~15 Add0~17 } "NODE_NAME" } } { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 8.897 ns Add0~18 4 COMB LCCOMB_X33_Y8_N20 1 " "Info: 4: + IC(0.000 ns) + CELL(0.506 ns) = 8.897 ns; Loc. = LCCOMB_X33_Y8_N20; Fanout = 1; COMB Node = 'Add0~18'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Add0~17 Add0~18 } "NODE_NAME" } } { "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 836 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.788 ns) + CELL(3.056 ns) 15.741 ns s\[2\] 5 PIN PIN_24 0 " "Info: 5: + IC(3.788 ns) + CELL(3.056 ns) = 15.741 ns; Loc. = PIN_24; Fanout = 0; PIN Node = 's\[2\]'" {  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.844 ns" { Add0~18 s[2] } "NODE_NAME" } } { "add4.vhd" "" { Text "D:/my_eda/add4/add4.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.189 ns ( 32.96 % ) " "Info: Total cell delay = 5.189 ns ( 32.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.552 ns ( 67.04 % ) " "Info: Total interconnect delay = 10.552 ns ( 67.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "15.741 ns" { a[0] Add0~15 Add0~17 Add0~18 s[2] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "15.741 ns" { a[0] a[0]~combout Add0~15 Add0~17 Add0~18 s[2] } { 0.000ns 0.000ns 6.764ns 0.000ns 0.000ns 3.788ns } { 0.000ns 0.945ns 0.596ns 0.086ns 0.506ns 3.056ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "103 " "Info: Allocated 103 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun May 13 11:03:57 2007 " "Info: Processing ended: Sun May 13 11:03:57 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}