any_div_1.fit.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

; 19                                           ; 0                           ;
; 20                                           ; 0                           ;
; 21                                           ; 0                           ;
; 22                                           ; 0                           ;
; 23                                           ; 0                           ;
; 24                                           ; 0                           ;
; 25                                           ; 0                           ;
; 26                                           ; 0                           ;
; 27                                           ; 0                           ;
; 28                                           ; 0                           ;
; 29                                           ; 0                           ;
; 30                                           ; 1                           ;
; 31                                           ; 0                           ;
; 32                                           ; 1                           ;
+----------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 9.00) ; Number of LABs  (Total = 4) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 1                           ;
; 2                                               ; 0                           ;
; 3                                               ; 1                           ;
; 4                                               ; 0                           ;
; 5                                               ; 0                           ;
; 6                                               ; 0                           ;
; 7                                               ; 0                           ;
; 8                                               ; 0                           ;
; 9                                               ; 0                           ;
; 10                                              ; 0                           ;
; 11                                              ; 0                           ;
; 12                                              ; 0                           ;
; 13                                              ; 0                           ;
; 14                                              ; 0                           ;
; 15                                              ; 0                           ;
; 16                                              ; 2                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 9.75) ; Number of LABs  (Total = 4) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 1                           ;
; 3                                           ; 1                           ;
; 4                                           ; 1                           ;
; 5                                           ; 0                           ;
; 6                                           ; 0                           ;
; 7                                           ; 0                           ;
; 8                                           ; 0                           ;
; 9                                           ; 0                           ;
; 10                                          ; 0                           ;
; 11                                          ; 0                           ;
; 12                                          ; 0                           ;
; 13                                          ; 0                           ;
; 14                                          ; 0                           ;
; 15                                          ; 0                           ;
; 16                                          ; 0                           ;
; 17                                          ; 0                           ;
; 18                                          ; 0                           ;
; 19                                          ; 0                           ;
; 20                                          ; 0                           ;
; 21                                          ; 0                           ;
; 22                                          ; 0                           ;
; 23                                          ; 0                           ;
; 24                                          ; 0                           ;
; 25                                          ; 0                           ;
; 26                                          ; 0                           ;
; 27                                          ; 0                           ;
; 28                                          ; 0                           ;
; 29                                          ; 0                           ;
; 30                                          ; 1                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Active Serial            ;
; Error detection CRC                          ; Off                      ;
; Reserve nCEO pin after configuration         ; As output driving ground ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Tue Mar 27 22:32:56 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off any_div_1 -c any_div_1
Info: Selected device EP2C5T144C6 for design "any_div_1"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C8T144C6 is compatible
Info: No exact pin location assignment(s) for 2 pins of 2 total pins
    Info: Pin clkout_3 not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Automatically promoted node clk (placed in PIN 17 (CLK0, LVDSCLK0p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  16 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  23 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  22 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 3.991 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X26_Y5; Fanout = 3; REG Node = 'cnt1[1]'
    Info: 2: + IC(0.934 ns) + CELL(0.414 ns) = 1.348 ns; Loc. = LAB_X27_Y6; Fanout