any_div_1.map.rpt

基于Quartus II FPGA/CPLD数字系统设计实例（VHDL源代码文件）

+----------------------------------+-----------------+-----------------+-----------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 46    ;
; Total combinational functions               ; 46    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 11    ;
;     -- 3 input functions                    ; 2     ;
;     -- <=2 input functions                  ; 33    ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 15    ;
;     -- arithmetic mode                      ; 31    ;
; Total registers                             ; 33    ;
; I/O pins                                    ; 2     ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 32    ;
; Total fan-out                               ; 181   ;
; Average fan-out                             ; 2.23  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; |any_div_1                 ; 46 (46)           ; 33 (33)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 2    ; 0            ; |any_div_1          ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 33    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------+
; Source assignments for Top-level Entity: |any_div_1 ;
+----------------+-------+------+---------------------+
; Assignment     ; Value ; From ; To                  ;
+----------------+-------+------+---------------------+
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[22]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[21]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[20]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[19]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[18]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[17]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[16]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[15]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[14]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[13]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[12]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[11]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[10]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[9]             ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[8]             ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[7]             ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[6]             ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[5]             ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[4]             ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[3]             ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[2]             ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[1]             ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[0]             ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[23]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[24]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[25]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[26]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[27]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[28]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[29]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[30]            ;
; POWER_UP_LEVEL ; Low   ; -    ; cnt1[31]            ;
+----------------+-------+------+---------------------+


+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |any_div_1 ;
+----------------+-------+--------------------------------------------------+
; Parameter Name ; Value ; Type                                             ;
+----------------+-------+--------------------------------------------------+
; n              ; 6     ; Integer                                          ;
+----------------+-------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Tue Mar 27 22:32:50 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off any_div_1 -c any_div_1
Info: Found 2 design units, including 1 entities, in source file any_div_1.vhd
    Info: Found design unit 1: any_div_1-A
    Info: Found entity 1: any_div_1
Info: Elaborating entity "any_div_1" for the top level hierarchy
Info: Implemented 48 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 46 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Mar 27 22:32:52 2007
    Info: Elapsed time: 00:00:04